cnt_12.vhd

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cnt_12 IS
PORT(CLK :IN STD_LOGIC;
     reset :IN STD_LOGIC;
      en :IN STD_LOGIC;
       co:OUT STD_ULOGIC;
      QL :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
      QH :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)
    );
END cnt_12;
ARCHITECTURE a OF cnt_12 IS
BEGIN
   PROCESS(CLK,reset)
   BEGIN
    IF reset='0'THEN
          QL<="0000";
          QH<="0000"; 
            co<='0';  
     ELSIF CLK'event AND clk='1'THEN
          
           IF QH="0001"AND QL="0001"THEN
             QL<="0000";
             QH<="0000";
              co<='1';
          ELSIF QL="1001"THEN
             QH<=QH+1;
             QL<="0000";
          ELSIF en='0'then
             QH<=QH;
             QL<=QL;
        ELSE QL<=QL+1;
            co<='0'; 
   END IF;
END IF;
END PROCESS;
END a;