v5_2.vhd

台湾全华科技VHDL教材实例

library ieee;
use ieee.std_logic_1164.all;

entity V5_2 is
port(sel   : in std_logic_vector(2 downto 0);
     a     : in  std_logic;
     b     : in  std_logic;
     c     : in  std_logic;
     d     : in  std_logic;
     o     : out std_logic);
end V5_2;

architecture a of V5_2 is
	
begin
    
    --o <= a when sel(2) = '0' else
    --	 b when sel(1) = '0' else
    --	 c when sel(0) = '0' else
    --	 d ;         
    	 
	o <= c when sel(0) = '0' else
    	 b when sel(1) = '0' else
    	 a when sel(2) = '0' else
    	 d ;
    	 
    
end a;