top.vhd

清华大学实验箱自带实验程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
    Port ( sysclk : in std_logic;
           resn : in std_logic;
           ps2clk : inout std_logic;
           ps2data : inout std_logic;
		     hsyncb: buffer std_logic;	-- horizontal (line) sync
		     vsyncb: buffer std_logic;	-- vertical (frame) sync
		     rgb: buffer std_logic_vector(7 downto 0));-- red,green,blue colors));
end top;

architecture Behavioral of top is

signal pblank,notrest: std_logic;	-- pipelined video blanking signal
--signal reset : std_logic;
signal clk : std_logic;
--signal sysclk_2 : std_logic;--VGA dot clock
--signal div_count : std_logic_vector(1 downto 0);
signal left_button : std_logic;
signal right_button : std_logic;
signal mousemov_x : std_logic_vector(9 downto 0);--mouse move at x
signal mousex : std_logic_vector(9 downto 0);--mouse x orridination
signal mousey : std_logic_vector(9 downto 0);
signal error_no_ack : std_logic;
signal read : std_logic;

signal hsyn,vsyn : std_logic;
signal hcnt : std_logic_vector(10 downto 0);
signal vcnt : std_logic_vector(9 downto 0);

signal hit_target : std_logic;
signal ballx : std_logic_vector(9 downto 0);--ball x orridination
signal bally : std_logic_vector(9 downto 0);--ball x orridination

signal backcolor : std_logic_vector(7 downto 0);
signal boardrgb : std_logic_vector(7 downto 0);
signal ballrgb : std_logic_vector(7 downto 0);
signal targetrgb : std_logic_vector(7 downto 0);
--signal rgbout : std_logic_vector(2 downto 0);

--clock ferquence
component count64 
    Port ( sysclk : in std_logic;
           reset : in std_logic;
           clkout : out std_logic);
end component;

--draw background
component frame 
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in std_logic_vector(10 downto 0);
           vcnt : in std_logic_vector(9 downto 0);
           backcolor : out std_logic_vector(7 downto 0));
end component;

--draw the movable board
component board 
    Port ( clk : in std_logic;
           reset : in std_logic;
			  hcnt : in std_logic_vector(10 downto 0);
           vcnt : in std_logic_vector(9 downto 0);
           location : in std_logic_vector(9 downto 0);
           boardrgb : out std_logic_vector(7 downto 0));
end component;

--draw the move ball
component ball 
    Port ( clk : in std_logic;
			  hcnt : in std_logic_vector(10 downto 0);
			  vcnt : in std_logic_vector(9 downto 0);
           reset : in std_logic;
           hit_target : in std_logic;
           --xsign : in std_logic;
           board_loc : in std_logic_vector(9 downto 0);
           --ball_loc : out std_logic_vector(9 downto 0);
			  ballx : out std_logic_vector(9 downto 0);
			  bally : out std_logic_vector(9 downto 0);
           ballrgb : out std_logic_vector(7 downto 0));
end component;

--draw target
component target 
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in std_logic_vector(10 downto 0);
           vcnt : in std_logic_vector(9 downto 0);
           mouse_x : in std_logic_vector(9 downto 0);
           ballx : in std_logic_vector(9 downto 0);
           bally : in std_logic_vector(9 downto 0);
           hit_target : out std_logic;
           targetrgb : out std_logic_vector(7 downto 0));
end component;

--mouse data receive
component mouse    
    Port (
	       clk : in std_logic;
          reset : in std_logic;
          ps2_clk : inout std_logic;
          ps2_data : inout std_logic;
          left_button : out std_logic;
          right_button : out std_logic;
			 mov_x : out std_logic_vector(9 downto 0);
          mousex : out std_logic_vector(9 downto 0);
          mousey : out std_logic_vector(9 downto 0);
          data_ready : out std_logic;-- rx_read_o
          --read : in std_logic; -- rx_read_ack_i
          error_no_ack : out std_logic
			 );
end component;

--show the data in CRT
component vgacore 
	port
	(
		reset : in std_logic;	-- reset
		clock : in std_logic;	-- VGA dot clock
		hsyncb : buffer std_logic;	-- horizontal (line) sync
		vsyncb : buffer std_logic;	-- vertical (frame) sync
      hcnt : buffer std_logic_vector(10 downto 0);	-- horizontal pixel counter
      vcnt : buffer std_logic_vector(9 downto 0)	-- vertical line counter
);
end component;

begin
notrest<=not resn;
  F: process(sysclk,notrest)
  begin
	  if notrest='1' then
		  pblank <= '0';
	  elsif (sysclk'event and sysclk='1') then
	    if (hcnt>799 or vcnt>599) then
	      pblank<='0';
	    else
		   pblank <= '1';
	    end if;
	  end if;
  end process;
  -- composite all the color
  --process (sysclk,resn)
  --begin
   -- if resn='1' then
	 --  rgb <= "00000000";
	 --elsif (sysclk'event and sysclk='1') then
	 --  if pblank='1' then
        rgb <= backcolor xor boardrgb xor ballrgb xor targetrgb;
	--	end if;
	 --end if;
  --end process;

  drawback: frame Port map
         ( clk => sysclk,
           reset => notrest,
           hcnt => hcnt,
           vcnt => vcnt,
           backcolor => backcolor);
  
  drawboard: board Port map
         ( clk => sysclk,
           reset => notrest,
			  hcnt => hcnt,
           vcnt => vcnt,
           location => mousex,
           boardrgb => boardrgb);

  drawball: ball Port map
         ( clk => sysclk,
			  hcnt => hcnt,
			  vcnt => vcnt,
           reset => notrest,
			  hit_target => hit_target,
           --xsign : in std_logic;
           board_loc => mousex,
           --ball_loc : out std_logic_vector(9 downto 0);
			  ballx => ballx,
			  bally => bally,
           ballrgb => ballrgb);

  drawtarget: target Port map
         ( clk => sysclk,
           reset => notrest,
           hcnt => hcnt,
           vcnt => vcnt,
           mouse_x => mousemov_x,
           ballx => ballx,
           bally => bally,
           hit_target => hit_target,
           targetrgb =>targetrgb);

  clocknum: count64 Port map
         ( sysclk => sysclk,
           reset => notrest,
           clkout => clk
			  );
 
  mousedata: mouse Port map
       (  clk => clk,
          reset => notrest,
          ps2_clk => ps2clk,
          ps2_data => ps2data,
          left_button => left_button,
          right_button => right_button,
			 mov_x => mousemov_x,
		    mousex => mousex,
		    mousey => mousey,
          data_ready => read,
          --read : in std_logic; -- rx_read_ack_i
          error_no_ack => error_no_ack
			 );

  showdata: vgacore port map
	(
		reset => notrest,
		clock => sysclk,
		hsyncb => hsyn,
		vsyncb => vsyn,
      hcnt => hcnt,
		vcnt => vcnt
   );

hsyncb <= hsyn;
vsyncb <= vsyn;
 
end Behavioral;