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Logic Analyzer 的代码
shizhi.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
SZ: OUT STD_LOGIC_VE
shizhi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
SZ: OUT STD_LOGIC_VE
shi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHI IS
PORT ( JW,RST: IN STD_LOGIC;
SZ: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XS: OUT S
zt.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ZT IS
PORT(GONG,RST : IN STD_LOGIC;
ZHUANG:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ZT;
ARCHITECTURE behav
zt.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ZT IS
PORT(GONG,RST : IN STD_LOGIC;
ZHUANG:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ZT;
ARCHITECTURE behav
f_m.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_M IS
PORT (RST,JW : IN STD_LOGIC;
FM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
CO : OUT STD_LOGI
zt.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ZT IS
PORT(GONG,RST : IN STD_LOGIC;
ZHUANG:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ZT;
ARCHITECTURE behav
shi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHI IS
PORT ( JW,RST: IN STD_LOGIC;
SZ: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XSL: OUT
shi.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHI IS
PORT ( JW,RST: IN STD_LOGIC;
SZ: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
XSL: OUT
lcd1602.vhd
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