shizhi.vhd.bak

可预置数字钟

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIZHI IS
PORT(RST,DIAO: IN STD_LOGIC;
     ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
     SZ: OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ));
END ;
ARCHITECTURE behav OF SHIZHI IS
BEGIN
PROCESS(DIAO,ZHUANG)
VARIABLE SZI:INTEGER RANGE 1 DOWNTO 0;
BEGIN
 IF RST='1' THEN SZI:=0;
ELSIF DIAO'EVENT AND DIAO='1' AND ZHUANG="100" THEN SZI:=SZI+1;
END IF;
IF SZI=0 THEN SZ<="00010001";
ELSE SZ<="00100011";
END IF;
END PROCESS ;
END behav;