zt.vhd

来自「可预置数字钟」· VHDL 代码 · 共 22 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ZT IS
PORT(GONG,RST : IN STD_LOGIC;
     ZHUANG:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ZT;
ARCHITECTURE behav OF ZT IS
BEGIN
PROCESS(GONG,RST)
VARIABLE Z :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF RST='1' THEN
Z:="000";
ELSIF GONG'EVENT AND GONG='1' THEN
 IF Z<"100" THEN Z:=Z+1;
 ELSE Z:="000";
END IF;
END IF;
ZHUANG<=Z;
END PROCESS;
END behav ;