f_m.vhd

可预置数字钟

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY F_M IS
  PORT (RST,JW : IN STD_LOGIC;
        FM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        CO : OUT STD_LOGIC );
END F_M;
ARCHITECTURE behav OF F_M IS
BEGIN
 PROCESS(JW,RST)
     VARIABLE   CQI : STD_LOGIC_VECTOR (7 DOWNTO 0);
 BEGIN
  IF RST='1' THEN CQI:= (OTHERS=>'0');
   ELSIF JW'EVENT AND JW='1' THEN
           IF CQI<"01011001" and CQI(3 downto 0)<"1001" THEN CQI:=CQI+1;CO<='0';
            ELSif CQI<"01011001" and CQI(3 downto 0)="1001" THEN CQI:=CQI+7; CO<='0';
              ELSE CQI:=(OTHERS=>'0');CO<='1';
              END IF;
           END IF;
           FM<=CQI;
       END PROCESS;
END behav;