shi.vhd

来自「可预置数字钟」· VHDL 代码 · 共 23 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHI IS
  PORT ( JW,RST: IN STD_LOGIC;
             SZ: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
             XS: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END SHI;
ARCHITECTURE behav OF  SHI IS
BEGIN
 P1:  PROCESS(JW,RST,SZ)
     VARIABLE   CQI : STD_LOGIC_VECTOR (7 DOWNTO 0);
 BEGIN
     IF RST='1' THEN CQI:= (OTHERS=>'0');
       ELSIF JW'EVENT AND JW='1' THEN
           IF CQI<SZ and CQI(3 downto 0)<"1001" THEN CQI:=CQI+1;
            ELSif CQI<SZ and CQI(3 downto 0)="1001" THEN CQI:=CQI+7; 
              ELSE CQI:=(OTHERS=>'0');
              END IF;
           END IF;
         XS<=CQI;  
       END PROCESS;
END behav;