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Logic Analyzer 的代码
cfg_regs.vhd
--*****************************************************************************
--* *
--* EuCore PCI-T32 - PCI Ta
muti_clock.vhd
--------------------------------------------
--library和package程序包声明
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee
sub4.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sub4 is
port(a : in std_logic_vector(3 downto 0);
b : in std_logic_vector (3 do
div.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div is
port(
a:in std_logic_vector(7 downto 0);
b:in std_logi
yima.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yima is
port(kin3,kin2,kin1,kin0: in std_logic;
sel2,sel1,sel0: in std_logic;
测试向量（test bench）和波形产生：vhdl实例---加法器源程序.txt
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
测试向量（test bench）和波形产生：vhdl实例---相应加法器的测试向量（test bench).txt
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------------------------------------------------------------
xspcore.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspuc.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
xspusb.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--