muti_clock.vhd

此为多功能数字电子钟的vhdl代码

--------------------------------------------
--library和package程序包声明
--------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------
--clock实体说明
--------------------------------------------
entity clock is
port(rst:in std_logic;--系统内部重置时钟信号
    clk:in std_logic;--系统时钟信号1024HZ
    alarm:in std_logic;--设置闹钟按钮信号
  stop:in std_logic;--设置定时器动作按钮
  ok:in std_logic;--设置完成确认键
  sec_tune:in std_logic;--秒钟调整按键信号
  min_tune:in std_logic;--分钟调整按键信号
  hour_tune:in std_logic;--时钟调整按键信号
  led_alarm:out std_logic;--闹钟设定时间到
  led_stop:out std_logic;--定时计数结束信号
  seg4:out std_logic_vector(6 downto 0);--分与秒4个数字多路扫描输出,可显示在七段显示器中
  p1,p2,p3,p4:out std_logic;--分与秒4个数字多路扫描电源激活输出
  seg2:out std_logic_vector(6 downto 0);--时的2个数字多路扫描输出,可显示在七段显示器中
  p5,p6:out std_logic);--时的2个数字多路扫描电源激活输出
end entity clock;
-------------------------------------------
--architecture模块开始
--定义功能模块block进行整体的信号传递
-------------------------------------------
architecture arch of clock is[separator]

---------------------------------------  
----div1024元件说明
----功能是转化为1HZ的信号输出
---------------------------------------
component div1024
  port ( clk: in std_logic;
       f1hz: out std_logic);
  end component;
---------------------------------------  
----count60元件说明
----功能是对分和秒进行计数
---------------------------------------
component count60
  port(carry: in std_logic;
        rst: in std_logic;
       times: out integer range 0 to 59;
        full: out std_logic);
  end component;
---------------------------------------  
----count24元件说明
----功能是对小时进行计数
--------------------------------------- 
component count24
  port(carry: in std_logic;
         rst: in std_logic;
       times: out integer range 0 to 23;
        full: out std_logic);
  end component;
---------------------------------------  
----alarm_set元件说明
----功能是设置定时
---------------------------------------
component alarm_set
  port(rst,hz1: in std_logic;
       alarm,ok: in std_logic;
       sec_tune: in std_logic;
       min_tune: in std_logic;
       hour_tune: in std_logic;
       sec,min: out integer range 0 to 59;
          hour: out integer range 0 to 23);
   end component;
---------------------------------------  
----stop_watch元件说明
----功能是对设置的定时进行计数
---------------------------------------

component stop_watch 
  port(ret,hz1: in std_logic;
          stop: in std_logic;
            ok:  in std_logic;
       sec_tune: in std_logic;
       min_tune: in std_logic;
      hour_tune: in std_logic;
      stop_sec,stop_min: out integer range 0 to 59;
              stop_hour:out integer range 0 to 23;
          index: out std_logic;
           disp: out std_logic);
   end component;
---------------------------------------  
----i60bcd元件说明
----功能是分秒十进制转化为二进制BCD码
--------------------------------------- 
component i60bcd
   port(interg: in integer range 0 to 59;
           ten: out std_logic_vector(3 downto 0);
           one: out std_logic_vector(3 downto 0));
   end component;
---------------------------------------  
----i24bcd元件说明
----功能是小时十进制转化为二进制BCD码
--------------------------------------- 
 
component i24bcd
   port(interg: in integer range 0 to 23;
           ten: out std_logic_vector(3 downto 0);
           one: out std_logic_vector(3 downto 0));
   end component;
---------------------------------------  
----scan4元件说明
----功能是分秒二进制BCD码在LED上显示
--------------------------------------- 

component scan4
   port(rst,clk: in std_logic;
        a,b,c,d: in std_logic_vector(6 downto 0);
        pa,pb,pc,pd: out std_logic;
        mux_out: out std_logic_vector(6 downto 0));
   end component;
----------------------------------------
----scan2元件说明
----功能是小时二进制BCD码在LED上显示
--------------------------------------- 

 component scan2
   port(rst,clk: in std_logic;
            a,b: in std_logic_vector(6 downto 0);
          pa,pb: out std_logic;
        mux_out: out std_logic_vector(6 downto 0));
   end component;
--------------------------------------
----bin2led元件说明
----功能是LED显示码
--------------------------------------- 


 component bin2led
    port(bin: in std_logic_vector(3 downto 0);
         led: out std_logic_vector(6 downto 0));
     end component;
-----------------------------------------
--结束程序包
----------------------------------------
signal hz1:std_logic;--1HZ的时钟信号
--正常显示时间
 signal n_sec,n_min:integer range 0 to 59;--正常的计数时间分与秒
 signal n_hour:integer range 0 to 23;--正常计数时间小时
--闹钟显示时间
 signal a_sec,a_min:integer range 0 to 59;--闹钟的计数时间分与秒
 signal a_hour:integer range 0 to 23;--闹钟计数时间小时
--定时显示时间
 signal s_sec,s_min:integer range 0 to 59;--定时的计数时间分与秒
 signal s_hour:integer range 0 to 23;--定时计数时间小时
--被选择输出的计数时间
 signal second,minute:integer range 0 to 59;--选择输出的计数时间分与秒
 signal hour:integer range 0 to 23;--选择输出计数时间小时
 signal sec_one,sec_ten,min_one,min_ten:std_logic_vector(3 downto 0);--个十位的BCD形式
 signal hour_one,hour_ten:std_logic_vector(3 downto 0);
--七段数码显示计数时间
 signal sec7_one,sec7_ten,min7_one,min7_ten:std_logic_vector(6 downto 0);
 signal hour7_one,hour7_ten:std_logic_vector(6 downto 0);
--计时与闹钟终止指针
 signal stop_index,alarm_index:std_logic;
 signal alarm_disp,stop_disp:std_logic;
--------------------------------------------
--signal定义结束
--begin开始
--------------------------------------------
begin
--------------------------------------------
--正常计时模块normal_counting
normal_counting:block
--input:rst,clk
--output:hz1,n_sec,n_min,n_hour
 signal full_sec:std_logic;--秒进位信号
 signal full_min:std_logic;--分进位信号
 signal full_hour:std_logic;--时进位信号
 begin
 u0:div1024 port map(clk=>clk,f1hz=>hz1);
 u1:count60 port map(rst=>rst,carry=>hz1,times=>n_sec,full=>full_sec);
 u2:count60 port map(rst=>rst,carry=>full_sec,times=>n_min,full=>full_min);
 u3:count24 port map(rst=>rst,carry=>full_min,times=>n_hour,full=>full_hour);
end block normal_counting;
--------------------------------------------
--定时器设定与计时功能模块stop_w
stop_w:block
--input:rst,hz1,stop,ok,sec_tune,min_tune,hour_tune
--output:s_sec,s_min,s_hour,stop_index
 begin
 u4:stop_watch port map(rst=>rst,hz1=>hz1,stop=>stop,ok=>ok,sec_tune=>
 sec_tune,min_tune=>min_tune,hour_tune=>hour_tune,stop_sec=>stop_sec,stop_min=>
 stop_min,stop_hour=>stop_hour,index=>stop_index,disp=>stop_disp);
 p1:process(rst,stop_index)
 begin
   if rst='1' then led_stop<='0';
   elsif rising_edge(stop_index) then
         led_stop<='1';
   end if;
  end process p1;
end block stop_w;

----------------------------------------------
--闹钟设定模块alarm_setting
alarm_setting:block
--input:rst,sec_tune,min_tune,hour_tune,alarm,ok
--output:a_sec,a_min,a_hour,alarm_index,led_alarm
 begin
 u5:alarm_set port map(rst=>rst,hz1=>hz1,alarm=>alarm,ok=>
 ok,sec_tune=>sec_tune,min_tune=>min_tune,hour_tune=>
 hour_tune,sec=>a_sec,min=>a_min,hour=>a_hour);
 p1:process(alarm,ok)
 begin
 if rst='1' then alarm_index<='0';
 elsif (alarm='1' and ok='1') then
   if(a_sec=n_sec and a_min=n_min and a_hour=n_hour)
     then alarm_index<='1';
     else alarm_index<='0';
   end if;
 end if;
 alarm_disp<=(alarm and not ok) and not alarm_index;
 end process p1;
 p2:process(rst,alarm_index)
 begin
   if rst='1' then led_alarm<='0';
   elsif rising_edge(alarm_index) then
     led_alarm<='1';
   end if;
 end process p2;
end block alarm_setting;


---------------------------------------------
--数码转换模块out
output:block
--input:clk,stop_disp,alarm_disp
--input:s_sec,s_min,s_hour,a_sec,a_min,a_hour,n_sec,n_min,n_hour
--output:second,minute,hour
 begin
 process(clk,stop_disp,alarm_disp)
   begin
   if rising_edge(clk) then
     if stop_disp='1' then second<=s_sec;
                 minute<=s_min;
                 hour<=s_hour;
   elsif alarm_disp='1' then second<=a_sec;
                  minute<=a_sec;
                  hour<=a_hour;
               else second<=n_sec;
                  minute<=n_min;
                  hour<=n_hour;
   end if;
 end if;
  end process;
--转换成BCD码
 u6:i60bcd port map(interg=>second,ten=>sec_ten,one=>sec_one);
 u7:i60bcd port map(interg=>minute,ten=>min_ten,one=>min_one);
 u8:i24bcd port map(interg=>hour,ten=>hour_ten,one=>hour_one);
end block output;
----------------------------------------
--扫描多路输出功能模块scan_display
scan_display:block
 begin
   u11:bin2led port map(bin=>sec_one,led=>sec7_one);
   u12:bin2led port map(bin=>sec_ten,led=>sec7_ten);
   u13:bin2led port map(bin=>min_one,led=>min7_one);
   u14:bin2led port map(bin=>min_ten,led=>min7_ten);
   u15:bin2led port map(bin=>hour_one,led=>hour7_one);

   u16:bin2led port map(bin=>hour_ten,led=>hour7_ten);
   u17:scan4 port map(rst=>rst,clk=>clk,a=>sec7_one,
             b=>sec7_ten,c=>min7_one,d=>min7_ten,
           mux_out=>seg4,pa=>p1,pb=>p2,pc=>p3,pd=>p4);
   u18:scan2 port map(rst=>rst,clk=>clk,a=>hour7_one,
             b=>hour7_ten,mux_out=>seg2,pa=>p5,pb=>p6);
end block scan_display;
------------------------------------------
--结束块
------------------------------------------
end architecture arch;

----div1024组件程序
----功能是转化为1HZ的信号输出
---------------------------------------
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;


 entity div1024 is
    port ( clk: in std_logic;
          f1hz: out std_logic);
    end;


 architecture arch of div1024  is
    signal count : integer range 0 to 1023;
    begin
  
    process(clk)
     begin
          if rising_edge(clk) then
             count<=count+1;
             if count>=1023 then f1hz<='1';
                            else f1hz<='0'; 
             end if;
           end if;
  end process;
  end arch;
---------------------------------------  
----count60组件程序
----功能是对分和秒进行计数
---------------------------------------
library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;


 entity count60 is 
      port(carry: in std_logic;
             rst: in std_logic;
           times: out integer range 0 to 59;
            full: out std_logic);
       end count60;


 architecture arch of count60  is
       signal time: integer range 0 to 59;
 begin 
       process(rst,carry) 
       begin
            if rst='1' then time<=0; full<='0';
            elsif rising_edge(carry) then
                    if time=59 then time<=0;
                                    full<='1';
                    else time<=time+1;
                        full<='0';
                    end if;
             end if;
        end process;
        times<=time;
  end arch;

---------------------------------------  
----count24组件程序
----功能是对小时进行计数
---------------------------------------