yima.vhd

利用FPGA编写的键盘译码程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yima is 
port(kin3,kin2,kin1,kin0: in std_logic;
          sel2,sel1,sel0: in std_logic;
                       Y: out std_logic_vector(3 downto 0));
end yima;

architecture yima_arch of yima is
signal a:std_logic_vector(3 downto 0);
signal b:std_logic_vector(2 downto 0);
signal c:std_logic;
begin
a<=kin3&kin2&kin1&kin0;
b<=sel2&sel1&sel0;
c<=kin3 and kin2 and kin2 and kin0;
  Y<="0000" when (b="000" and a="1110" ) else  --0
     "0110" when (b="000" and a="1101" ) else  --6
     "0001" when (b="001" and a="1110" ) else  --1
     "0111" when (b="001" and a="1101" ) else  --7 
     "0010" when (b="010" and a="1110" ) else  --2
     "0011" when (b="011" and a="1110" ) else  --3
     "1000" when (b="100" and a="1101" ) else  --8
     "1001" when (b="101" and a="1101" ) else  --9
     "0100" when (b="110" and a="1110" ) else  --4
     "0101" when (b="111" and a="1110" ) else  --5
     "0000";
end yima_arch;