sub4.vhd

用VHDL语言实现通用计算器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity sub4 is
port(a : in std_logic_vector(3 downto 0);
b : in std_logic_vector (3 downto 0);
ci : in std_logic;
S : out std_logic_vector(3 downto 0);
co :out std_logic);
end sub4;

architecture rt1 of sub4 is
component adder is
port 
(a: in std_logic;
 b: in std_logic;
 ci: in std_logic;
 s : out std_logic;
 co: out std_logic);
end component;
signal btem: std_logic_vector( 3 downto 0);
signal ctem: std_logic_vector( 4 downto 0);
signal stem: std_logic_vector (3 downto 0);
begin
btem(3 downto 0 ) <=not b( 3 downto 0);
ctem(0)<=not ci;
g1: for i in 0 to 3 generate 
add: adder port map (a(i),btem(i),ctem(i),stem(i),ctem(i+1));
end generate;
s(3 downto 0)<=stem( 3 downto 0);
co<= not ctem(4);
end rt1;