div.vhd

用VHDL语言实现通用计算器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity div is
   port(
       a:in std_logic_vector(7 downto 0);
       b:in std_logic_vector(3 downto 0);
       clk: in std_logic;
       str: in std_logic;
       s:   out std_logic_vector(3 downto 0);
       y:   out std_logic_vector(3 downto 0)
       );
end div;

architecture rt1 of div is

component sub4 is
 port(
	a:in std_logic_vector(3 downto 0);
    b:in std_logic_vector(3 downto 0);
	ci: in  std_logic;
	s:  out std_logic_vector(3 downto 0);
    co: out std_logic
     );

end component;

type state_type is (start, one,two,three,eror);
signal state: state_type;
signal ain:   std_logic_vector(7 downto 0);
signal bin:   std_logic_vector(3 downto 0);
signal atem:  std_logic_vector(3 downto 0);
signal btem:  std_logic_vector(3 downto 0);
signal stem:  std_logic_vector(3 downto 0);
signal citem: std_logic;
signal cotem: std_logic;

begin

p2:process(clk)
variable n: integer range 0 to 3;--yiwei

begin
if clk'event and clk='1' then
	case state is
when start=>
if str='1' then
state<=one;
atem(3 downto 0)<=a(7 downto 4);
btem(3 downto 0)<=b(3 downto 0);
ain(7 downto 0)<=a(7 downto 0);
bin(3 downto 0)<=b(3 downto 0);
end if;

when one=>
if cotem='0' then
---
state<=eror;
else
ain(3 downto 1)<=ain(2 downto 0);
ain(0)<=not cotem;
atem(3 downto 0)<=ain(6 downto 3);
state<=two;
end if;

when two=>
if n=2 then
state<=three;
n:=0;
else
state<=two;
n:=n+1;
end if;
if cotem='0' then
atem(3 downto 1)<=stem(2 downto 0);
else
atem(3 downto 1)<=atem( 2 downto 0);
end if;

ain(3 downto 1)<=ain(2 downto 0);
ain(0)<=not cotem;
atem(0)<=ain(3);
	when three=>
	s(3 downto 1)<=ain(2 downto 0);
    s(0)<=not cotem;
    if cotem='0' then
    y(3 downto 0)<=stem(3 downto 0);
    else 
    y(3 downto 0)<=atem(3 downto 0);
    end if;
    atem(3 downto 0)<="0";
    btem(3 downto 0)<="0";
    state<=start;

when eror=>
state<=start;
atem(3 downto 0)<="0";
btem(3 downto 0)<="0";

    end case;
end if;
end process p2;

citem<='0';
u1:sub4 port map(atem,btem,citem,stem,cotem);
end rt1;