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Logic Analyzer 的代码
min4_e.vhd
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---- ----
---- min4_e.vhd
trellis1_e.vhd
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---- ----
---- trellis1_e.vhd
multi8x8.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH IS --选通与门模块
PORT (ABIN:IN STD_LOGIC; --与门开关
DIN:IN STD_LOGIC_VECTOR (7 DOWNTO 0); --8位输入
D
ps2_vhdl.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps2 is
port
(
kd:in std_logic;
clkin : in std_logic;
kc:in std_logic;
led:out std_logic_ve
spi.vhd
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity spi is --
port( sclk:in std_logic;
cs:in std_logic;
read:in std_logic;
nia.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity nia is
port (clk, ena: in std_logic;
dn, qn: out std_logic_vector(3 downto 0);
yf: out std_
jishu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0);
co_sec: out std_logic
jishu1.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu1 is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0);
co_sec: out std_logi
jishu2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu2 is
port(clk1: in std_logic;
ge1,shi1: out std_logic_vector(3 downto 0));
end jishu2;
architect
serial_generatedinstance.vhd
--------------------------------------------------
-- Model : 8051 Behavioral Model,
-- VHDL Entity mc8051.serial.generatedInstance
--
-- Author : Michael Mayer (