multi8x8.vhd

节约资源型 8位*8位 运算VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ANDARITH  IS    								--选通与门模块
   PORT (ABIN:IN STD_LOGIC;    						--与门开关
         DIN:IN STD_LOGIC_VECTOR (7 DOWNTO 0);    	--8位输入 
        DOUT:OUT STD_LOGIC_VECTOR (7 DOWNTO 0));	--8位输出
END ENTITY ANDARITH;
ARCHITECTURE ART OF ANDARITH IS 
BEGIN
    PROCESS (ABIN,DIN) IS
    BEGIN

FOR I IN 0 TO 7 LOOP    		
           --循环,分别完成8位数据与一位控制位的与操作
           DOUT (I)<=DIN (I)AND ABIN;    
        END LOOP;
     END PROCESS;
END ARCHITECTURE ART;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG16B IS    								--16位锁存器
  PORT (CLK:IN STD_LOGIC;   						--锁存信号
        CLR:IN STD_LOGIC;    					                        --清零信号

       D:IN STD_LOGIC_VECTOR (8 DOWNTO 0); 		
                              --8位数据输入
        Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));	                  --16位数据输出
END ENTITY REG16B;
ARCHITECTURE ART OF REG16B IS 
  SIGNAL R16S:STD_LOGIC_VECTOR(15 DOWNTO 0);	                   --16位寄存器设置
BEGIN
PROCESS (CLK,CLR) IS
BEGIN
     IF CLR = '1' THEN R16S<= "0000000000000000";
       	--异步复位信号
     ELSIF CLK'EVENT AND CLK = '1' THEN			--时钟到来时,锁存输入值
          R16S(6 DOWNTO 0)<=R16S(7 DOWNTO 1);		--右移低8位
        R16S(15 DOWNTO 7)<=D;    				--将输入锁到高8位
      END IF;
END PROCESS;
      Q<=R16S;
END ARCHITECTURE ART;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; 
ENTITY SREG8B IS     								--8位右移寄存器
   PORT (CLK:IN STD_LOGIC; 
		LOAD:IN STD_LOGIC;
         DIN:IN STD_LOGIC_VECTOR(7DOWNTO 0);
         QB:OUT STD_LOGIC);
END ENTITY SREG8B;
ARCHITECTURE ART OF SREG8B IS 
  SIGNAL REG8:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
   PROCESS (CLK,LOAD) IS
   BEGIN
   IF CLK'EVENT AND CLK= '1' THEN
    IF LOAD = '1' THEN REG8<=DIN;    				--装载新数据
ELSE REG8(6 DOWNTO 0)<=REG8(7 DOWNTO 1);		--数据右移
    END IF;
   END IF;
END PROCESS;
QB<= REG8(0);    								--输出最低位
END ARCHITECTURE ART;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ARICTL IS    								--乘法运算控制器
 PORT ( CLK:IN STD_LOGIC;     START:IN  STD_LOGIC;
        CLKOUT:OUT STD_LOGIC; RSTALL:OUT STD_LOGIC;
        ARIEND:OUT STD_LOGIC);
END ENTITY ARICTL;
ARCHITECTURE ART OF ARICTL IS 
SIGNAL CNT4B:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  RSTALL<=START;
  PROCESS (CLK,START) IS
  BEGIN
    IF START = '1' THEN CNT4B<= "0000";    	
      elsif clk'event and clk='1' then                                          --高电平清零计数器ELSIF CLK'EVENT AND CLK = '1' THEN
      IF CNT4B<=8 THEN    					
                  --小于则计数,等于8表明乘法运算已经结束
        CNT4B<=CNT4B+1;
 END IF;
    END IF;
END PROCESS;
PROCESS (CLK,CNT4B,START) IS

BEGIN
    IF START = '0' THEN
      IF CNT4B<=8 THEN    	--乘法运算正在进行
         CLKOUT <=CLK;    ARIEND<= '0';
      ELSE CLKOUT <= '0';   ARIEND<= '1';
                                     	--运算已经结束
     END IF;
   ELSE CLKOUT <=CLK;    ARIEND<= '0';
   END IF;
END PROCESS;
END ARCHITECTURE ART;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER4B IS    								--4位二进制并行加法器
PORT(C4: IN STD_LOGIC;    					--低位来的进位
   A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);    --4位加数
  B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4位被加数
  S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--4位和
CO4: OUT STD_LOGIC);    			--进位输出
END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
SIGNAL S5:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL A5,B5: STD_LOGIC_VECTOR(4 DOWNTO 0);

BEGIN 
 A5<='0'& A4;    	
              --将4位加数矢量扩为5位,为进位提供空间
 B5<='0'& B4;    	
              --将4位被加数矢量扩为5位,为进位提供空间
 S5<=A5+B5+C4 ;
 S4<=S5(3 DOWNTO 0);
       CO4<=S5(4);
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS    --由4位二进制并行加法器级联而成的8位二进制加法器
PORT(Cin:IN STD_LOGIC;
          A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          CO:OUT STD_LOGIC);
END ENTITY ADDER8B;
ARCHITECTURE ART OF ADDER8B IS
COMPONENT ADDER4B IS  
         --对要调用的元件ADDER4B的界面端口进行定义
PORT(C4:IN STD_LOGIC;
          A4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO4:OUT STD_LOGIC);
END COMPONENT ADDER4B;
SIGNAL SC:STD_LOGIC;    --4位加法器的进位标志
BEGIN
U1:ADDER4B    --例化(安装)一个4位二进制加法器U1
PORT MAP(C4=>Cin,A4=>A(3 DOWNTO 0),B4=>B(3 DOWNTO 0),S4=>S(3 DOWNTO 0),CO4=>SC);
U2:ADDER4B    --例化(安装)一个4位二进制加法器U2
PORT MAP(C4=>SC,A4=>A(7 DOWNTO 4),B4=>B(7 DOWNTO 4),
S4=>S (7 DOWNTO 4),CO4=>CO);
END ARCHITECTURE ART;


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;    	
ENTITY MULTI8X8 IS									--8位乘法器顶层设计
  PORT(CLK:IN STD_LOGIC;
        START:IN STD_LOGIC;		
       	--乘法启动信号,高电平复位与加载,低电平运算
        A:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 	--8位被乘数
        B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);  	  
                                         --8位乘数     
 ARIEND:OUT STD_LOGIC;    					                                     --乘法运算结束标志位
 DOUT:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
                            	--16位乘积输出
END ENTITY MULTI8X8;
ARCHITECTURE ART OF MULTI8X8 IS 
COMPONENT ARICTL IS   				
                            --待调用的乘法控制器端口定义
PORT(CLK:IN STD_LOGIC;START:IN STD_LOGIC;
          CLKOUT:OUT STD_LOGIC;RSTALL:OUT STD_LOGIC;
          ARIEND:OUT STD_LOGIC);
END COMPONENT ARICTL;
COMPONENT ANDARITH IS   --待调用的控制与门端口定义
      PORT(ABIN:IN STD_LOGIC;
            DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            DOUT:OUT STD_LOGIC_VECTOR( 7 DOWNTO 0) );
END COMPONENT ANDARITH;
COMPONENT ADDER8B IS   	
   PORT(Cin:IN STD_LOGIC;
          A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			S:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
          CO:OUT STD_LOGIC);
end component;                     --待调用的8位加法器端口定义
COMPONENT SREG8B IS   			
                      --待调用的8位右移寄存器端口定义
      PORT (CLK:IN STD_LOGIC; LOAD:IN STD_LOGIC;
         DIN:IN STD_LOGIC_VECTOR(7DOWNTO 0);
         QB:OUT STD_LOGIC);
end component;
COMPONENT REG16B IS   			
                       --待调用的16右移寄存器端口定义
PORT (CLK:IN STD_LOGIC;   						--锁存信号
        CLR:IN STD_LOGIC;    					                        --清零信号

D:IN STD_LOGIC_VECTOR (8 DOWNTO 0); 		
                              --8位数据输入
        Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
end component;
   			
      
SIGNAL S1:STD_LOGIC; 
SIGNAL S2:STD_LOGIC;
SIGNAL S3:STD_LOGIC;
SIGNAL S4:STD_LOGIC;
SIGNAL S5:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL S6:STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL S7:STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
DOUT<=S7;S1<= '0';
      U1:ARICTL PORT MAP(CLK=>CLK,   START=>START,
                             CLKOUT=>S2, RSTALL=>S3, ARIEND=>ARIEND);   
      U2:SREG8B PORT MAP(CLK=>S2, LOAD=>S3,
                              DIN=>A, QB=>S4);
      U3:ANDARITH PORT MAP(ABIN=>S4,DIN=>B,DOUT=>S5);
      U4:ADDER8B PORT MAP(CIN=>S1,A=>S7(15 DOWNTO 8),B=>S5,S=>S6(7 DOWNTO 0),CO =>S6(8));
      U5:REG16B PORT MAP(CLK =>S2,CLR=>S3,  D=>S6, Q=>S7);
END ARCHITECTURE ART;