jishu.vhd

MAX+plus II 9.23 Baseline

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu is
port(clk1: in std_logic;
     ge1,shi1: out std_logic_vector(3 downto 0);
     co_sec: out std_logic);
end jishu;

architecture seconds of jishu is
signal jin1: std_logic_vector(3 downto 0);
signal jin : std_logic;
begin
  process(clk1)
     variable ge,shi: std_logic_vector(3 downto 0):="0000";     
    begin            
      if(clk1'event and clk1='1') then
         ge1<=ge; 
         ge:=ge+1;
         ge1<=ge;
         jin<='0';
         if ge="1010" then
            ge:="0000";
            ge1<=ge;
            shi:=shi+1;
            shi1<=shi;
            if shi="0110" then
               shi:="0000";
               shi1<=shi;
               jin1<=jin1+1;
               jin<='1';
            end if;  
         end if;
       end if;
  end process;
  co_sec<=jin;
end;