ps2_vhdl.txt

利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ps2 is
port
  (
    kd:in std_logic;
    clkin : in std_logic;
    kc:in std_logic;
    led:out std_logic_vector(4 downto 0)
   
   );
end entity ps2;

architecture one of ps2 is


signal clk:std_logic;
signal num : std_logic_vector(4 downto 0);
signal m: std_logic_vector( 9 downto 0 );
begin
 
 process(clkin)

  begin
    if clkin'event and clkin = '1' then 
       if kc = '0' then 
         clk <= kc;
        else 
       
         clk <= '1';
      end if;
    end if;
end process;

  process(clk,kd,m)

  begin
   if clk'event and clk = '0' then
        m <= kd & m( 9 downto 1 );
      
      
     end if;
  end process;


 process(clk,kd,m)

  begin
    if clk'event and clk = '1' then
       case m(7 downto 0) is
                    when "00010110" => NUM <= "00001"; --1
				  	when "00011110" => NUM <= "00010"; --2
				  	when "00100110" => NUM <= "00011"; --3
				  	when "00100101" => NUM <= "00100"; --4
				  	when "00101110" => NUM <= "00101"; --5
				  	when "00110110" => NUM <= "00110"; --6
				  	when "00111101" => NUM <= "00111"; --7
					when "00111110" => NUM <= "01000";--8
					when "01000110" => NUM <= "01001";--9
				  	when "01000101" => NUM <= "00000";--0
					when "00011100" => NUM <= "01010";--a
					when "00110010" => NUM <= "01011";--b
					when "00100001" => NUM <= "01100";--c
					when "00100011" => NUM <= "01101";--d
					when "00100100" => NUM <= "01110";
					when "00101011" => NUM <= "01111";
					when others     => NUM <= "11111";
				end case;
		end if;
		end process;
led <= num;
end one;