jishu2.vhd

MAX+plus II 9.23 Baseline

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity jishu2 is
port(clk1: in std_logic;
     ge1,shi1: out std_logic_vector(3 downto 0));
end jishu2;

architecture hours of jishu2 is
begin
  process(clk1)
     variable ge,shi: std_logic_vector(3 downto 0):="0000";     
    begin            
      if(clk1'event and clk1='1') then
         ge1<=ge; 
         ge:=ge+1;
         ge1<=ge;
         if ge="1010" then
            ge:="0000";
            ge1<=ge;
            shi:=shi+1;
            shi1<=shi;
          elsif shi="0010"and ge="0100" then
               shi:="0000";
              
               shi1<=shi;
             
                ge:="0000";
                ge1<=ge;  
                    
          end if;
       end if;
  end process;
end;