代码搜索结果
找到约 10,000 项符合
Logic Analyzer 的代码
packfp.vhd
--
-- VHDL Architecture HAVOC.PackFP.PackFP
--
-- Created:
-- by - Guillermo
-- at - ITESM, 09:57:50 07/16/03
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Bui
fplzc.vhd
--modified 2007,03 v1
--modified 2007,04,09 v2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY FPlzc IS
PORT(
word : IN std_logic_vector (26 DOWNTO 0);
mico8.vhm
--
-- Written by Synplicity
-- Product Version "Version 9.0L1"
-- Program "Synplify", Mapper "9.0.0, Build 139R"
-- Fri Mar 14 11:39:56 2008
--
--
-- Written by Synplify version 9.0.0, Build
mico8.vhd
-- VHDL model created from schematic mico8.sch -- Mar 14 11:39:50 2008
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library ecp2;
use ecp2.components.all;
-- synopsys t
led_m8.vhd
-----------------------------------------------------------------------
-- LED_M8.vhd
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT
ahb_package.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package ahb_package is
-----------------------------------------------------------------------------
-- Generic contants
---
mc8051_ramx_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
mc8051_rom_.vhd
-------------------------------------------------------------------------------
-- --
-- X X XXXXXX XXXX
uart.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:37:27 03/13/09
-- Design Name:
-- Module Name: uart - B
top.vhf
-- VHDL model created from top.sch - Wed Jun 20 18:35:50 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcompo