mico8.vhm

Lattice 超精简8位软核CPU--Mico8

--
-- Written by Synplicity
-- Product Version "Version 9.0L1"
-- Program "Synplify", Mapper "9.0.0, Build 139R"
-- Fri Mar 14 11:39:56 2008
--

--
-- Written by Synplify version 9.0.0, Build 139R
-- Fri Mar 14 11:39:56 2008
--

-- No definition of black box work.pmi_distributed_spram_work_mico8_schematic_1.syn_black_box
-- No definition of black box work.pmi_addsub_work_mico8_schematic_0.syn_black_box
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity isp8_io_cntl is
port(
  MicoAddr : out std_logic_vector(7 downto 0);
  MicoDOut : out std_logic_vector(7 downto 0);
  dout_rd : in std_logic_vector(7 downto 0);
  dout_rb : in std_logic_vector(7 downto 0);
  Mico8_Instr_7 :  in std_logic;
  Mico8_Instr_6 :  in std_logic;
  Mico8_Instr_5 :  in std_logic;
  Mico8_Instr_4 :  in std_logic;
  Mico8_Instr_3 :  in std_logic;
  Mico8_Instr_1 :  in std_logic;
  Mico8_Instr_0 :  in std_logic;
  addr_cyc_int_1_1 :  out std_logic;
  GND :  in std_logic;
  Mico_RD_c :  out std_logic;
  Mico_WR_c :  out std_logic;
  nReset_c :  in std_logic;
  ext_mem_wr :  out std_logic;
  MicoCLK :  in std_logic;
  iels_ls :  in std_logic;
  addr_cyc :  in std_logic;
  ext_addr_cyc_int_Q :  in std_logic;
  iels_ie :  in std_logic);
end isp8_io_cntl;

architecture beh of isp8_io_cntl is
  signal EXT_ADDR_4 : std_logic_vector(7 downto 0);
  signal EXT_DOUT_QN : std_logic_vector(7 downto 0);
  signal EXT_ADDR_QN : std_logic_vector(7 downto 0);
  signal EXT_IO_WR_2 : std_logic ;
  signal EXT_MEM_WR_1_1 : std_logic ;
  signal EXT_IO_RD_1_1 : std_logic ;
  signal EXT_MEM_WR_QN : std_logic ;
  signal EXT_IO_WR_QN : std_logic ;
  signal EXT_IO_RD_QN : std_logic ;
  signal UN6_EXPORT_I : std_logic ;
  signal N_51 : std_logic ;
  signal NN_1 : std_logic ;
  signal VCC : std_logic ;
begin
  EXT_IO_WR_2 <= (not Mico8_Instr_0 and iels_ie and ext_addr_cyc_int_Q) or 
	  (not Mico8_Instr_0 and iels_ie and addr_cyc);
  EXT_MEM_WR_1_1 <= (not Mico8_Instr_0 and iels_ls and ext_addr_cyc_int_Q) or 
	  (not Mico8_Instr_0 and iels_ls and addr_cyc);
  EXT_IO_RD_1_1 <= (ext_addr_cyc_int_Q and Mico8_Instr_0 and iels_ie) or 
	  (addr_cyc and Mico8_Instr_0 and iels_ie);
  EXT_ADDR_4(5) <= (dout_rb(5) and not iels_ls and not iels_ie) or 
	  (dout_rb(5) and Mico8_Instr_1);
  EXT_ADDR_4(6) <= (dout_rb(6) and not iels_ls and not iels_ie) or 
	  (dout_rb(6) and Mico8_Instr_1);
  EXT_ADDR_4(7) <= (dout_rb(7) and not iels_ls and not iels_ie) or 
	  (dout_rb(7) and Mico8_Instr_1);
  EXT_MEM_WR_REG: FD1S3AX port map (
      D => EXT_MEM_WR_1_1,
      CK => MicoCLK,
      Q => ext_mem_wr);
  EXT_IO_WR_REG: FD1S3AX port map (
      D => EXT_IO_WR_2,
      CK => MicoCLK,
      Q => Mico_WR_c);
  EXT_IO_RD_REG: FD1S3AX port map (
      D => EXT_IO_RD_1_1,
      CK => MicoCLK,
      Q => Mico_RD_c);
  \EXT_DOUT[0]_REG\: FD1S3AX port map (
      D => dout_rd(0),
      CK => MicoCLK,
      Q => MicoDOut(0));
  \EXT_DOUT[1]_REG\: FD1S3AX port map (
      D => dout_rd(1),
      CK => MicoCLK,
      Q => MicoDOut(1));
  \EXT_DOUT[2]_REG\: FD1S3AX port map (
      D => dout_rd(2),
      CK => MicoCLK,
      Q => MicoDOut(2));
  \EXT_DOUT[3]_REG\: FD1S3AX port map (
      D => dout_rd(3),
      CK => MicoCLK,
      Q => MicoDOut(3));
  \EXT_DOUT[4]_REG\: FD1S3AX port map (
      D => dout_rd(4),
      CK => MicoCLK,
      Q => MicoDOut(4));
  \EXT_DOUT[5]_REG\: FD1S3AX port map (
      D => dout_rd(5),
      CK => MicoCLK,
      Q => MicoDOut(5));
  \EXT_DOUT[6]_REG\: FD1S3AX port map (
      D => dout_rd(6),
      CK => MicoCLK,
      Q => MicoDOut(6));
  \EXT_DOUT[7]_REG\: FD1S3AX port map (
      D => dout_rd(7),
      CK => MicoCLK,
      Q => MicoDOut(7));
  \EXT_ADDR[0]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(0),
      CK => MicoCLK,
      Q => MicoAddr(0));
  \EXT_ADDR[1]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(1),
      CK => MicoCLK,
      Q => MicoAddr(1));
  \EXT_ADDR[2]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(2),
      CK => MicoCLK,
      Q => MicoAddr(2));
  \EXT_ADDR[3]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(3),
      CK => MicoCLK,
      Q => MicoAddr(3));
  \EXT_ADDR[4]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(4),
      CK => MicoCLK,
      Q => MicoAddr(4));
  \EXT_ADDR[5]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(5),
      CK => MicoCLK,
      Q => MicoAddr(5));
  \EXT_ADDR[6]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(6),
      CK => MicoCLK,
      Q => MicoAddr(6));
  \EXT_ADDR[7]_REG\: FD1S3AX port map (
      D => EXT_ADDR_4(7),
      CK => MicoCLK,
      Q => MicoAddr(7));
  addr_cyc_int_1_1 <= not addr_cyc and not ext_addr_cyc_int_Q;
  EXT_ADDR_4(0) <= (dout_rb(0) and UN6_EXPORT_I) or 
	  (not UN6_EXPORT_I and Mico8_Instr_3);
  EXT_ADDR_4(1) <= (dout_rb(1) and UN6_EXPORT_I) or 
	  (not UN6_EXPORT_I and Mico8_Instr_4);
  EXT_ADDR_4(2) <= (dout_rb(2) and UN6_EXPORT_I) or 
	  (not UN6_EXPORT_I and Mico8_Instr_5);
  EXT_ADDR_4(3) <= (dout_rb(3) and UN6_EXPORT_I) or 
	  (not UN6_EXPORT_I and Mico8_Instr_6);
  EXT_ADDR_4(4) <= (dout_rb(4) and UN6_EXPORT_I) or 
	  (not UN6_EXPORT_I and Mico8_Instr_7);
  UN6_EXPORT_I <= (not iels_ie and not iels_ls) or 
	  (Mico8_Instr_1);
  NN_1 <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity isp8_flow_cntl is
port(
  din_rd1 : in std_logic_vector(7 downto 0);
  Mico8_Instr_12 :  in std_logic;
  Mico8_Instr_15 :  in std_logic;
  Mico8_Instr_14 :  in std_logic;
  Mico8_Instr_13 :  in std_logic;
  Mico8_Instr_11 :  in std_logic;
  Mico8_Instr_10 :  in std_logic;
  Mico8_Instr_8 :  in std_logic;
  Mico8_Instr_7 :  in std_logic;
  Mico8_Instr_6 :  in std_logic;
  Mico8_Instr_5 :  in std_logic;
  Mico8_Instr_4 :  in std_logic;
  Mico8_Instr_3 :  in std_logic;
  Mico8_Instr_2 :  in std_logic;
  Mico8_Instr_1 :  in std_logic;
  Mico8_Instr_0 :  in std_logic;
  VCC :  in std_logic;
  N_301_i :  out std_logic;
  cout_alu_u_0_1 :  in std_logic;
  N_140 :  in std_logic;
  Mico_Int_c :  in std_logic;
  update_c_i :  in std_logic;
  setc :  in std_logic;
  clrc :  in std_logic;
  call :  in std_logic;
  N_303_i :  out std_logic;
  prom_addr_1_16_i_i_a2_s_0_N_5 :  in std_logic;
  br_enb_0_a2_0_0 :  in std_logic;
  setz :  in std_logic;
  sc :  in std_logic;
  update_z_1 :  in std_logic;
  update_z_0 :  in std_logic;
  un1_br0 :  in std_logic;
  ca0 :  in std_logic;
  iels :  in std_logic;
  instr_l2_3 :  in std_logic;
  N_53_i :  out std_logic;
  N_51_i :  out std_logic;
  N_307_i :  out std_logic;
  N_306_i :  out std_logic;
  N_305_i :  out std_logic;
  N_304_i :  out std_logic;
  N_302_i :  out std_logic;
  instr_l1_3 :  in std_logic;
  sp_we_1_i_o2_N_14_i :  out std_logic;
  iret :  in std_logic;
  GND :  in std_logic;
  addr_cyc_int_1_1 :  in std_logic;
  carry_flag :  out std_logic;
  ext_addr_cyc_int_Q :  out std_logic;
  clri_i :  in std_logic;
  INTAck_c :  out std_logic;
  g0_7 :  in std_logic;
  intr_reg0 :  out std_logic;
  addr_cyc :  out std_logic;
  data_cyc_int :  out std_logic;
  re :  in std_logic;
  nReset_c :  in std_logic;
  zero_flag :  out std_logic;
  MicoCLK :  in std_logic);
end isp8_flow_cntl;

architecture beh of isp8_flow_cntl is
  signal STACK_PTR : std_logic_vector(3 downto 0);
  signal STACK_PTR_QN : std_logic_vector(3 downto 0);
  signal PC : std_logic_vector(8 downto 0);
  signal PC_QN : std_logic_vector(8 downto 0);
  signal ADDR_JMP_REG : std_logic_vector(8 downto 0);
  signal ADDR_JMP_REG_QN : std_logic_vector(8 downto 0);
  signal UN1_ADDR_CYC_INT_I_A2_1 : std_logic_vector(2 to 2);
  signal DOUT_STACK : std_logic_vector(8 downto 0);
  signal PC_INT : std_logic_vector(8 downto 0);
  signal UN1_ADDR_CYC_INT_I_A2_D : std_logic_vector(2 to 2);
  signal UN1_ADDR_CYC_INT_I_A2_D_0_1 : std_logic_vector(2 to 2);
  signal N_77 : std_logic ;
  signal N_285_I : std_logic ;
  signal ZERO_FLAG_QN : std_logic ;
  signal UN1_STACK_PTR_AXB0 : std_logic ;
  signal UN1_STACK_PTR_AXBXC1 : std_logic ;
  signal UN1_STACK_PTR_AXBXC2 : std_logic ;
  signal UN1_STACK_PTR_AXBXC3 : std_logic ;
  signal RET_REG : std_logic ;
  signal RET_REG_QN : std_logic ;
  signal N_55_I : std_logic ;
  signal N_57_I : std_logic ;
  signal DATA_CYC_INT_INT_17 : std_logic ;
  signal N_59_I : std_logic ;
  signal N_61_I : std_logic ;
  signal N_63_I : std_logic ;
  signal N_65_I : std_logic ;
  signal N_68_I : std_logic ;
  signal N_70_I : std_logic ;
  signal N_73_I : std_logic ;
  signal INTR_REG0_1 : std_logic ;
  signal INTR_REG0_QN : std_logic ;
  signal N_20 : std_logic ;
  signal INTR_ACK_INT_QN : std_logic ;
  signal N_287_I : std_logic ;
  signal IE_FLAG : std_logic ;
  signal IE_FLAG_QN : std_logic ;
  signal UN3_EXT_ADDR_CYC_INT_0_A2 : std_logic ;
  signal EXT_ADDR_CYC_INT_QN : std_logic ;
  signal N_18 : std_logic ;
  signal DATA_CYC_INT_QN : std_logic ;
  signal CARRY_FLAG_INT_1_1 : std_logic ;
  signal N_286_I : std_logic ;
  signal CARRY_FLAG_INT_QN : std_logic ;
  signal N_280_I : std_logic ;
  signal ADDR_CYC_INT_16 : std_logic ;
  signal BR_ENB_REG : std_logic ;
  signal BR_ENB_REG_QN : std_logic ;
  signal ADDR_CYC_INT_QN : std_logic ;
  signal N_24_I : std_logic ;
  signal UN1_STACK_PTR_P4 : std_logic ;
  signal N_157 : std_logic ;
  signal ZERO_FLAG_1_I_A2_0_0 : std_logic ;
  signal INTR_REG0_1_0_A2_4_TZ_0_0 : std_logic ;
  signal N_110 : std_logic ;
  signal N_111 : std_logic ;
  signal N_112 : std_logic ;
  signal N_113 : std_logic ;
  signal N_114 : std_logic ;
  signal N_115 : std_logic ;
  signal N_116 : std_logic ;
  signal N_117 : std_logic ;
  signal INTR_REG0_INT_15 : std_logic ;
  signal INTACK_C_INT_14 : std_logic ;
  signal PROM_ADDR_I_0_M5_0_A2_0 : std_logic ;
  signal ZERO_FLAG_1_I_A2_0_5 : std_logic ;
  signal CARRY_FLAG_INT_12 : std_logic ;
  signal ZERO_FLAG_INT_18 : std_logic ;
  signal SP_WE_1_I_O2_M8_I_1 : std_logic ;
  signal ZERO_FLAG_1_I_A2_0_6 : std_logic ;
  signal N_108 : std_logic ;
  signal EXT_ADDR_CYC_INT_Q_INT_13 : std_logic ;
  signal INTR_REG0_1_1_TZ : std_logic ;
  signal N_145 : std_logic ;
  signal SP_WE_1_I_O2_N_14_I_INT_11 : std_logic ;
  signal N_129 : std_logic ;
  signal INTR_REG0_1_4 : std_logic ;
  signal PUSHED_ZERO : std_logic ;
  signal N_22 : std_logic ;
  signal N_24 : std_logic ;
  signal INTR_REG0_1_0_A2_2 : std_logic ;
  signal N_125 : std_logic ;
  signal PUSHED_CARRY : std_logic ;
  signal UN1_STACK_PTR_AXBXC3_1 : std_logic ;
  signal PC_INT_CRY_6 : std_logic ;
  signal PC_INT_CRY_7_0_COUT : std_logic ;
  signal PC_INT_CRY_4 : std_logic ;
  signal PC_INT_CRY_2 : std_logic ;
  signal PC_INT_CRY_0 : std_logic ;
  signal PC_INT_CRY_0_0_S0 : std_logic ;
  signal PC_INT_CRY_0_0_S1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component pmi_distributed_spram_work_mico8_schematic_1
    port(
      Address : in std_logic_vector(3 downto 0);
      Data : in std_logic_vector(10 downto 0);
      Clock :  in std_logic;
      ClockEn :  in std_logic;
      WE :  in std_logic;
      Reset :  in std_logic;
      Q : out std_logic_vector(10 downto 0)  );
  end component;
begin
  ZERO_FLAG_REG: FD1P3AX port map (
      D => N_77,
      SP => N_285_I,
      CK => MicoCLK,
      Q => ZERO_FLAG_INT_18);
  \STACK_PTR[0]_REG\: FD1S3AX port map (
      D => UN1_STACK_PTR_AXB0,
      CK => MicoCLK,
      Q => STACK_PTR(0));
  \STACK_PTR[1]_REG\: FD1S3AX port map (
      D => UN1_STACK_PTR_AXBXC1,
      CK => MicoCLK,
      Q => STACK_PTR(1));
  \STACK_PTR[2]_REG\: FD1S3AX port map (
      D => UN1_STACK_PTR_AXBXC2,
      CK => MicoCLK,
      Q => STACK_PTR(2));
  \STACK_PTR[3]_REG\: FD1S3AX port map (
      D => UN1_STACK_PTR_AXBXC3,
      CK => MicoCLK,
      Q => STACK_PTR(3));
  RET_REG_REG: FD1S3AX port map (
      D => re,
      CK => MicoCLK,
      Q => RET_REG);
  \PC[0]_REG\: FD1P3AX port map (
      D => N_55_I,
      SP => DATA_CYC_INT_INT_17,
      CK => MicoCLK,
      Q => PC(0));
  \PC[1]_REG\: FD1P3AX port map (
      D => N_57_I,