mico8.vhd

Lattice 超精简8位软核CPU--Mico8

-- VHDL model created from schematic mico8.sch -- Mar 14 11:39:50 2008

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library ecp2;
use ecp2.components.all;
-- synopsys translate_on

entity MICO8 is
      Port ( Mico_WR : Out   std_logic;
              CLK_IN : In    std_logic;
              INTAck : Out   std_logic;
             Mico_RD : Out   std_logic;
             Mico_Int : Out   std_logic;
              nReset : In    std_logic;
             Ser_Out : Out   std_logic;
               Valid : Out   std_logic;
                LEDs : Out   std_logic_vector (7 downto 0);
                 PWM : Out   std_logic;
                 TXD : Out   std_logic;
              LCD_EN : Out   std_logic;
               LCD_D : Out   std_logic_vector (7 downto 0);
              LCD_RS : Out   std_logic;
             RC5_PWR : Out   std_logic;
               Segm1 : Out   std_logic_vector (6 downto 0);
               Segm2 : Out   std_logic_vector (6 downto 0);
                DIP8 : In    std_logic_vector (7 downto 0);
               RXD_A : In    std_logic;
               RXD_B : In    std_logic;
               X2CLK : Out   std_logic );

end MICO8;

architecture SCHEMATIC of MICO8 is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal      N_1 : std_logic;
   signal      N_2 : std_logic;
   signal     IRQ2 : std_logic;
   signal     IRQ1 : std_logic;
   signal     IRQ0 : std_logic;
   signal      One : std_logic;
   signal     Zero : std_logic;
   signal Mico_Int_DUMMY : std_logic;
   signal Mico_RD_DUMMY : std_logic;
   signal INTAck_DUMMY : std_logic;
   signal  MicoCLK : std_logic;
   signal    Reset : std_logic;
   signal Mico_WR_DUMMY : std_logic;
   signal MicoDOut : std_logic_vector (7 downto 0);
   signal MicoAddr : std_logic_vector (7 downto 0);
   signal Mico8_Instr : std_logic_vector (17 downto 0);
   signal  MicoDin : std_logic_vector (7 downto 0);
   signal  Peri0_D : std_logic_vector (7 downto 0);
   signal   Per1_D : std_logic_vector (7 downto 0);
   signal   Per2_D : std_logic_vector (7 downto 0);
   signal Mico8_RomAddr : std_logic_vector (8 downto 0);

   component ISP8_CFG5
      Port (     clk : In    std_logic;
             ext_io_din : In    std_logic_vector (7 downto 0);
             ext_mem_ready : In    std_logic;
               instr : In    std_logic_vector (17 downto 0);
                intr : In    std_logic;
               rst_n : In    std_logic;
             data_cyc : InOut std_logic;
             ext_addr : Out   std_logic_vector (7 downto 0);
             ext_addr_cyc : Out   std_logic;
             ext_io_dout : Out   std_logic_vector (7 downto 0);
             ext_io_rd : Out   std_logic;
             ext_io_wr : Out   std_logic;
             intr_ack : Out   std_logic;
             prom_addr : Out   std_logic_vector (8 downto 0);
                Zero : Out   std_logic );
   end component;

   component RX_UART_M8
      Port (     Clk : In    std_logic;
               Reset : In    std_logic;
                 RXD : In    std_logic;
             Data_Out : Out   std_logic_vector (7 downto 0);
             Data_Ready : Out   std_logic );
   end component;

   component DIP8_M8
      Port (     Clk : In    std_logic;
                DIP8 : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
             Data_Out : Out   std_logic_vector (7 downto 0);
             Data_Ready : Out   std_logic );
   end component;

   component INT_HANDL_M8
      Port (     Clk : In    std_logic;
                IRQ0 : In    std_logic;
                IRQ1 : In    std_logic;
                IRQ2 : In    std_logic;
                IRQ3 : In    std_logic;
             Mico8_Addr : In    std_logic_vector (7 downto 0);
             Mico8_IntAck : In    std_logic;
             Mico8_RD : In    std_logic;
             Peri0_Data : In    std_logic_vector (7 downto 0);
             Peri1_Data : In    std_logic_vector (7 downto 0);
             Peri2_Data : In    std_logic_vector (7 downto 0);
             Peri3_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
             Mico8_Data : Out   std_logic_vector (7 downto 0);
             Mico8_INT : Out   std_logic );
   end component;

   component SEG7_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
             Segm_Out1 : Out   std_logic_vector (6 downto 0);
             Segm_Out2 : Out   std_logic_vector (6 downto 0) );
   end component;

   component LCD_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
             LCD_Data : Out   std_logic_vector (7 downto 0);
             LCD_Enable : Out   std_logic;
              LCD_RS : Out   std_logic );
   end component;

   component TX_UART_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
              TX_Ack : Out   std_logic;
                 TXD : Out   std_logic );
   end component;

   component LED_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
             LEDs_Out : Out   std_logic_vector (7 downto 0) );
   end component;

   component PWM_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
             PWM_Out : Out   std_logic );
   end component;

   component SEROUT_M8
      Port (    Addr : In    std_logic_vector (7 downto 0);
                 Clk : In    std_logic;
             Mico8_Data : In    std_logic_vector (7 downto 0);
               Reset : In    std_logic;
                  WR : In    std_logic;
             Ser_Out : Out   std_logic;
               Valid : Out   std_logic );
   end component;

   component PROGPROM
      Port ( Address : In    std_logic_vector (8 downto 0);
             OutClock : In    std_logic;
             OutClockEn : In    std_logic;
               Reset : In    std_logic;
                   Q : Out   std_logic_vector (17 downto 0) );
   end component;

   component MY_PLL
      Port (     CLK : In    std_logic;
               RESET : In    std_logic;
               CLKOK : Out   std_logic;
               CLKOP : Out   std_logic;
                LOCK : Out   std_logic );
   end component;

   component SYS_CNTRL
      Port (  nReset : In    std_logic;
                 One : Out   std_logic;
             RC5_PWR : Out   std_logic;
               Reset : Out   std_logic;
                Zero : Out   std_logic );
   end component;

begin

   Mico_WR <= Mico_WR_DUMMY;
   INTAck <= INTAck_DUMMY;
   Mico_RD <= Mico_RD_DUMMY;
   Mico_Int <= Mico_Int_DUMMY;

   I78 : ISP8_CFG5
      Port Map ( clk=>MicoCLK,
                 ext_io_din(7 downto 0)=>MicoDin(7 downto 0),
                 ext_mem_ready=>One,
                 instr(17 downto 0)=>Mico8_Instr(17 downto 0),
                 intr=>Mico_Int_DUMMY, rst_n=>nReset, data_cyc=>N_1,
                 ext_addr(7 downto 0)=>MicoAddr(7 downto 0),
                 ext_addr_cyc=>open,
                 ext_io_dout(7 downto 0)=>MicoDOut(7 downto 0),
                 ext_io_rd=>Mico_RD_DUMMY, ext_io_wr=>Mico_WR_DUMMY,
                 intr_ack=>INTAck_DUMMY,
                 prom_addr(8 downto 0)=>Mico8_RomAddr(8 downto 0),
                 Zero=>N_2 );
   I79 : RX_UART_M8
      Port Map ( Clk=>MicoCLK, Reset=>Reset, RXD=>RXD_A,
                 Data_Out(7 downto 0)=>Peri0_D(7 downto 0),
                 Data_Ready=>IRQ0 );
   I77 : RX_UART_M8
      Port Map ( Clk=>MicoCLK, Reset=>Reset, RXD=>RXD_B,
                 Data_Out(7 downto 0)=>Per2_D(7 downto 0),
                 Data_Ready=>IRQ2 );
   I76 : DIP8_M8
      Port Map ( Clk=>MicoCLK, DIP8(7 downto 0)=>DIP8(7 downto 0),
                 Reset=>Reset, Data_Out(7 downto 0)=>Per1_D(7 downto 0),
                 Data_Ready=>IRQ1 );
   I75 : INT_HANDL_M8
      Port Map ( Clk=>MicoCLK, IRQ0=>IRQ0, IRQ1=>IRQ1, IRQ2=>IRQ2,
                 IRQ3=>Zero,
                 Mico8_Addr(7 downto 0)=>MicoAddr(7 downto 0),
                 Mico8_IntAck=>INTAck_DUMMY, Mico8_RD=>Mico_RD_DUMMY,
                 Peri0_Data(7 downto 0)=>Peri0_D(7 downto 0),
                 Peri1_Data(7 downto 0)=>Per1_D(7 downto 0),
                 Peri2_Data(7 downto 0)=>Per2_D(7 downto 0),
                 Peri3_Data(7 downto 0)=>Per2_D(7 downto 0),
                 Reset=>Reset,
                 Mico8_Data(7 downto 0)=>MicoDin(7 downto 0),
                 Mico8_INT=>Mico_Int_DUMMY );
   I74 : SEG7_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY,
                 Segm_Out1(6 downto 0)=>Segm1(6 downto 0),
                 Segm_Out2(6 downto 0)=>Segm2(6 downto 0) );
   I71 : LCD_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY,
                 LCD_Data(7 downto 0)=>LCD_D(7 downto 0),
                 LCD_Enable=>LCD_EN, LCD_RS=>LCD_RS );
   I72 : TX_UART_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY, TX_Ack=>open, TXD=>TXD );
   I69 : LED_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY,
                 LEDs_Out(7 downto 0)=>LEDs(7 downto 0) );
   I70 : PWM_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY, PWM_Out=>PWM );
   I65 : SEROUT_M8
      Port Map ( Addr(7 downto 0)=>MicoAddr(7 downto 0), Clk=>MicoCLK,
                 Mico8_Data(7 downto 0)=>MicoDOut(7 downto 0),
                 Reset=>Reset, WR=>Mico_WR_DUMMY, Ser_Out=>Ser_Out,
                 Valid=>Valid );
   I61 : PROGPROM
      Port Map ( Address(8 downto 0)=>Mico8_RomAddr(8 downto 0),
                 OutClock=>MicoCLK, OutClockEn=>N_1, Reset=>N_2,
                 Q(17 downto 0)=>Mico8_Instr(17 downto 0) );
   I47 : MY_PLL
      Port Map ( CLK=>CLK_IN, RESET=>Reset, CLKOK=>MicoCLK, CLKOP=>X2CLK,
                 LOCK=>open );
   I54 : SYS_CNTRL
      Port Map ( nReset=>nReset, One=>One, RC5_PWR=>RC5_PWR,
                 Reset=>Reset, Zero=>Zero );

end SCHEMATIC;