代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/268098/11154439
vhd sr_tuner.vhd
-- sample rate tuner
-- sampling frequency = 1 / srate
-- 'srate' represents the time elapsed between two sample pulses
-- 'srate' is increased/decreased exponentially as the 'smpupbtn'/'smpdownbtn
www.eeworm.com/read/268098/11154463
vhd osc_ctrl.vhd
-- oscilloscope control
-- the main purpose of the osc_ctrl is to
-- 1. control the sampling rate of the A/D converter
-- 2. control the display of the signal
--
www.eeworm.com/read/267978/11158399
vhd sysctrl0.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sysctrl0 is
port(
clk1:in std_logic;
clk2:in std_logic;
clk3:in std_logic;
clk
www.eeworm.com/read/267833/11160959
vhd tg68_fast.vhd
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
www.eeworm.com/read/412996/11170598
vhd regfile.vhd
--****************************************************************************************************
-- Register file for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 23.01.2003
--******
www.eeworm.com/read/412996/11170628
vhd alu.vhd
--****************************************************************************************************
-- ALU for ARM core
-- Designed by Ruslan Lepetenok
-- Modified 16.12.2002
--****************
www.eeworm.com/read/412996/11170636
vhd controllogic.vhd
--****************************************************************************************************
-- Control logic for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 11.02.20
www.eeworm.com/read/412996/11170655
vhd bbusmultiplexer.vhd
--****************************************************************************************************
-- B bus multiplexer for ARM7TDMI-S processor
-- Designed by Ruslan Lepetenok
-- Modified 04.1
www.eeworm.com/read/412996/11170673
vhd datamux.vhd
--****************************************************************************************************
-- Data multiplexer for ARM memory sybsistem
-- Designed by Ruslan Lepetenok
-- Modified 07.12
www.eeworm.com/read/267559/11174970
vhd fifo_exp1.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo89 is
Port ( clk : in std_logic;
rst : in std_logic;