osc_ctrl.vhd

罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, PhD提供的示波器开发全文挡及C,VHDL代码.

-- oscilloscope control
-- the main purpose of the osc_ctrl is to 
--              1. control the sampling rate of the A/D converter
--              2. control the display of the signal
--              3. display parameters of the oscilloscope and let the user modify them
--              4. switch between modes of operation of the oscilloscope

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity osc_ctrl is
  port (rst         : in std_logic; -- resets the oscilloscope to its initial state
        mclk        : in std_logic;
        hold        : in std_logic; -- freezes the display
        trigger_en  : in std_logic; -- enables triggered mode
        sample      : out std_logic; -- tells the acquisition module to start the conversion
        rdy         : in std_logic; -- the controller is notified when the converision is done
        data7       : in std_logic; -- needed to determine the triggering event
        addr        : out std_logic_vector(9 downto 0); -- video memory address (write address)
        smpdownbtn  : in std_logic; -- decreases the sampling rate
        smpupbtn    : in std_logic; -- increases the sampling rate
        an          : out std_logic_vector(3 downto 0);
        ssg         : out std_logic_vector(7 downto 0));
end osc_ctrl;

architecture Behavioral of osc_ctrl is

   COMPONENT sr_tuner
   PORT( ssg	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          an	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0); 
          srate	:	OUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          dn	:	IN	STD_LOGIC; 
          up	:	IN	STD_LOGIC; 
          rst	:	IN	STD_LOGIC; 
          mclk	:	IN	STD_LOGIC);
   END COMPONENT;

signal srate      : std_logic_vector(15 downto 0); -- sampling rate
signal samplecnt  : std_logic_vector (15 downto 0):=(others =>'0'); 
signal addrcnt    : std_logic_vector(9 downto 0) :=(others =>'0');
signal trigger    : std_logic := '0'; 
signal d7         : std_logic;

begin

-- up and down buttons modify the sampling rate (srate)
sample_rate_tuner: sr_tuner port map(
        mclk => mclk, 
        rst => rst, 
        up => smpupbtn, 
        dn => smpdownbtn,
        srate => srate, 
        ssg => ssg, 
        an => an 
        );

-- d7 is a latch containing the previous value of data7
process(rdy)
begin

  if (rdy'event and rdy = '1') then
    d7 <= data7;
  end if;

end process;       

-- data7 is compared to its previous value (d7) and at the right moment 
-- triggers the display reset (trigger <= '1') so the signal appears to be stable on the screen
process(rdy, data7, d7, trigger_en)
begin

  if (trigger_en = '0' or (data7 and d7) = '1') then
    trigger <= '0';
  elsif (rdy'event and rdy = '0') then 
    if (data7 = '1' and d7 = '0') then
      trigger <= '1'; -- trigger is enabled only on the rising edge of the signal, at 0 passing
    end if;
  end if;

end process;      

-- addrcnt specifies the write address of the video memory
-- as new samples arrive (rdy ='0') they are stored in the memory in a sequential order
process (rst, rdy)
begin

  if (rst = '1') then
    addrcnt <= (others => '0');
  elsif (rdy'event and rdy = '1') then -- data is written in the memory on the falling edge of rdy so the address has to be ready earlier,
                                       -- on the rising edge
    if (addrcnt < 639) then
      addrcnt <= addrcnt + 1; -- samples are stored sequentially
    elsif (hold = '1') then
      addrcnt <= "1010000000"; -- freezes the display
    elsif (trigger_en = '0' or trigger = '1') then -- equivalent to (trigger_en='0' or (trigger_en='1' and trigger='1'))
      addrcnt <= (others => '0'); -- the next waveform is traced on the same position of the screen so the image appears to be still
    end if;
  end if;

end process;  

addr <=addrcnt; -- write address for the memory

-- 'samplecnt' counts from 0 to 'srate'; srate is variable and can be modified with the up/dn buttons
process(mclk, samplecnt, srate)
begin

  if (samplecnt >= srate) then
    samplecnt <= (others => '0');
  elsif (mclk'event and mclk = '1') then
    samplecnt <= samplecnt + 1 ;
  end if;

end process;         

-- sample tells the acquisition module to start the conversion
process(samplecnt, srate)
begin

  if (samplecnt = X"0000") then
    sample <= '0';  -- activate
  elsif (samplecnt >= srate) then -- wait until the right amount of time has passed 
    sample <= '1'; -- inactivate
  end if;

end process;

end Behavioral;