📄 sysctrl0.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity sysctrl0 is
port(
clk1:in std_logic;
clk2:in std_logic;
clk3:in std_logic;
clk4:in std_logic;
nao:in std_logic;
set:in std_logic;
sel:in std_logic;
adj:in std_logic;
nao0:out std_logic;
clock:out std_logic;
adjo:out std_logic;
adjst:out std_logic_vector(4 downto 0);
disable:out std_logic_vector(5 downto 0);
tsel:out std_logic_vector(2 downto 0);
dis6:out std_logic_vector(5 downto 0));
end;
architecture a of sysctrl0 is
signal dispb:std_logic_vector(2 downto 0);
signal blink:std_logic_vector(5 downto 0);
signal tflag:std_logic;
signal tmpset:std_logic;
signal tmpsel:std_logic;
signal tmpnao:std_logic;
signal kkk:std_logic;
begin
process(clk4)
begin
if clk4'event and clk4='0' then
if tmpset='1' then clock<=clk1;
else clock<='0';
end if;
end if;
end process;
process (clk4)
variable q6:integer range 0 to 7;
begin
if(clk4'event and clk4='1') then
q6:=q6+1;
if (q6=6) then
q6:=0;
end if;
case q6 is
when 0=>dis6<="111110";
when 1=>dis6<="111101";
when 2=>dis6<="111011";
when 3=>dis6<="110111";
when 4=>dis6<="101111";
when 5=>dis6<="011111";
when others=>dis6<="111111";
end case;
end if;
dispb<=conv_std_logic_vector(q6,3);
tsel<=dispb;
end process;
process(clk3)
begin
if clk3'event and clk3='1' then
tmpnao<=nao;
tmpset<=set;
tmpsel<=sel;
end if;
end process;
process(clk2)
begin
if clk2'event and clk2='1' then
tflag<=not tflag;
end if;
end process;
process(tmpsel,tmpset,tmpnao)
begin
if tmpset='1' then blink<="000001";
elsif tmpsel'event and tmpsel='0' then
if blink="000000" then blink<="000001";
elsif blink="000001" then blink<="000010";
elsif blink="000010" then blink<="000100";
elsif blink="000100" then blink<="001000";
elsif blink="001000" then blink<="110000";
else blink<="000001";
end if;
end if;
end process;
disable<=blink when tflag='1' and tmpset='0' else "000000";
nao0<=tmpnao;
process(clk3)
begin
if clk3'event and clk3='0' then
if tmpset='0' then
adjst<=blink(4 downto 0);
else adjst<="00000";
end if;
end if;
end process;
process(clk3,tmpset)
begin
if tmpset='1' then
adjo<='0';
elsif clk3'event and clk3='1' then
adjo<=not adj;
end if;
end process;
end a;
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