sr_tuner.vhd

罗马尼亚克鲁日工程大学Mircea D&#259 b&acirc can, PhD提供的示波器开发全文挡及C,VHDL代码.

-- sample rate tuner
-- sampling frequency = 1 / srate
-- 'srate' represents the time elapsed between two sample pulses
-- 'srate' is increased/decreased exponentially as the 'smpupbtn'/'smpdownbtn' is pressed
-- 'srate' starts at a specific value (250 ns) then it increases (500, 1000, etc.)
-- 'srate' must be at all times in the [250 ns, 4000 ns] interval
-- 'uspdiv' represents the 'microseconds per division' on the screen of the oscilloscope
-- 'uspdiv' is a linear function of 'srate': 'uspdiv' = 'srate' x period(mclk) x (nr of pixels between two vertical grid lines)
-- 'uspdiv' is displayed on the 7 segment display
-- the value shown is the 'microseconds per division' in decimal format

-- to calculate the frequency of a signal count the divisions that make up a period (e.g. 6.25)
-- multiply that value with the value shown on the 7 segment display (e.g. 1600)
-- divide 1 with the number obtained ( 1 / 6.25 x 1600 ) this is the frequency of the signal in MHz
-- multiply the value with 10^6 to obtain the frequency in Hz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sr_tuner is
   PORT( ssg	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          an	:	OUT	STD_LOGIC_VECTOR (3 DOWNTO 0); 
          srate	:	OUT	STD_LOGIC_VECTOR (15 DOWNTO 0); 
          dn	:	IN	STD_LOGIC; 
          up	:	IN	STD_LOGIC; 
          rst	:	IN	STD_LOGIC; 
          mclk	:	IN	STD_LOGIC);
end sr_tuner;

architecture Behavioral of sr_tuner is

	COMPONENT rate2div
	PORT(
		srate : IN std_logic_vector(15 downto 0);          
		uspdiv : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
	COMPONENT ssgdisp
	PORT(
		rst : IN std_logic;
		mclk : IN std_logic;
		xval : IN std_logic_vector(15 downto 0);          
		ssg : OUT std_logic_vector(7 downto 0);
		an : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;
  COMPONENT btnpush
   PORT( mclk	:	IN	STD_LOGIC; 
          up	:	IN	STD_LOGIC; 
          dn	:	IN	STD_LOGIC; 
          en	:	OUT	STD_LOGIC);
   END COMPONENT;

signal ce : std_logic;
signal load : std_logic;
signal uord : std_logic;
signal sr : std_logic_vector(15 downto 0);
signal xval : std_logic_vector(15 downto 0);

begin 

-- increases/decreases the 'srate' according to the input (up/dn) buttons
process (mclk)
begin
  if (mclk'event and mclk='1') then
    if (load='1') then
      sr <= X"00FA";
    elsif (ce = '1') then
      if (up = '1') then
        sr <= sr(14 downto 0) & '0';
      else
        sr <= '0' & sr(15 downto 1);
      end if;
    end if;
  end if;
end process;

load <= rst or not sr(7);
srate <= sr;
uord <= up or dn;

-- this process takes care that the value of 'srate' is incremented only once, when the button is pushed
process(mclk, uord)
variable push_event : boolean := false;
begin
  if (uord = '0') then
    ce <= '0';
    push_event := false;
  elsif (mclk'event and mclk='1') then
    if (push_event = false) then
      ce <= '1';
      push_event := true;
    else
      ce <= '0';
    end if;
 end if;
end process;

-- this unit calculates the values of 'microseconds per division' to be displayed according to 'srate'
	srate2uspdiv: rate2div PORT MAP(
		srate => sr,
		uspdiv => xval
	);

-- the 7 segment display shows the value of 'microseconds per division'
	ssg_display: ssgdisp PORT MAP(
		rst => rst,
		mclk => mclk,
		xval => xval,
		ssg => ssg,
		an => an
	);





end Behavioral;