fifo_exp1.vhd

在ISE环境下用VHDL写的8*9FIFO

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo89 is
    Port ( clk : in std_logic;
           rst : in std_logic;
           rd : in std_logic;
           wr : in std_logic;
           rdinc : in std_logic;
           wrinc : in std_logic;
           rdptrclr : in std_logic;
           wrptrclr : in std_logic;
           data_in : in std_logic_vector(8 downto 0);
           data_out : out std_logic_vector(8 downto 0));
end fifo89;

-- clk: used to synchronize the buffers;
-- rst: reset the buffers
-- rd: when valid, the output buffers are enabled;
-- wr: when valid, write register with 9-bit width is permitted; 
-- rdinc: read counter enabled;
-- wrinc: write counter enabled;
-- rdptrclr: reset read counter, pointing to the first register for
-- read purpose;
-- wrptrclr: reset write counter, pointing to the first register for
-- write purpose;
-- data_in: data inputs with 9-bit width to the FIFOs;
-- data_out: data outputs with 9-bit width from the FIFOs.

architecture Behavioral of fifo89 is
	type fifo_array is array(7 downto 0) of std_logic_vector(8 downto 0);
	signal fifo: fifo_array;
	signal wrptr, rdptr: std_logic_vector(2 downto 0);
	signal en: std_logic_vector( 7 downto 0);
	signal dmuxout: std_logic_vector(8 downto 0);

begin
-- fifo register_array:
reg_array: process (rst, clk)
	begin
		if rst = '1' then
			for i in 7 downto 0 loop
				fifo(i) <= (others => '0'); -- aggregate
			end loop;
		elsif (clk'event and clk = '1') then
			if wr = '1' then
				for i in 7 downto 0 loop
					if en(i) = '1' then
						fifo(i) <= data_in;
					else
						fifo(i) <= fifo(i);
					end if;
				end loop;
			end if;
		end if;
	end process;

-- read pointer
read_count: process (rst, clk)
	begin
		if rst = '1' then
			rdptr <= (others => '0');
		elsif (clk'event and clk = '1') then
			if rdptrclr = '1' then
				rdptr <= (others => '0');
			elsif rdinc = '1' then
				rdptr <= rdptr + 1;
			end if;
		end if;
	end process;

-- write pointer
write_count: process (rst, clk)
	begin
		if rst = '1' then
			wrptr <= (others => '0');
		elsif (clk'event and clk = '1') then
			if wrptrclr = '1' then
				wrptr <= (others => '0');
			elsif wrinc = '1' then
				wrptr <= wrptr + 1;
			end if;
		end if;
	end process;

-- 8:1 output data mux
with rdptr select
	dmuxout <= fifo(0) when "000",
				  fifo(1) when "001",
				  fifo(2) when "010",
				  fifo(3) when "011",
				  fifo(4) when "100",
				  fifo(5) when "101",
				  fifo(6) when "110",
				  fifo(7) when others;

-- FIFO register selector decoder
with wrptr select
	en <= "00000001" when "000",
			"00000010" when "001",
			"00000100" when "010",
			"00001000" when "011",
			"00010000" when "100",
			"00100000" when "101",
			"01000000" when "110",
			"10000000" when others;

-- three-state control of outputs
three_state: process (rd, dmuxout)
	begin
		if rd = '1' then
			data_out <= dmuxout;
		else
			data_out <= (others => 'Z');
		end if;
	end process;

end Behavioral;