代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/312754/13605455
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/312401/13611790
vhd usb_fpga.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY USB_FPGA IS
GENERIC (
FIFOLENTH : integer := 1024; --FIFO长度2048
FIFOWITH
www.eeworm.com/read/311483/13630138
vhd cornaa.vhd
library ieee;
use ieee.std_logic_1164.all;
entity cornaa is
port(clk,k1,k0,clr,load,lc:in std_logic; --k1,k0分别为代表1和0的按键开关
lt:inout std_logic; --load为设置密
www.eeworm.com/read/310768/13644269
vhd speakera.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
ENTITY Speakera IS
PORT ( clk: IN STD_LOGIC ;
Tone: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SpkS:OUT STD_
www.eeworm.com/read/310741/13644717
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k
www.eeworm.com/read/309346/13673737
vhd br_gen.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity br_gen is
generic(divisor: integer := 26);
port(
sysclk:in std_logic;
sel :in std_
www.eeworm.com/read/308751/13693677
vho ram.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation
www.eeworm.com/read/307578/13720266
vhd ctrl.vhd
--CTRL.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTRL IS
PORT ( DATA_N: IN STD_LOGIC_VECTOR(3 DOWNTO 0); --数字
www.eeworm.com/read/307575/13720338
vhd cont60.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cont60 is
port(ci :in std_logic;
nreset :in std_logic;
load :in std_logic;
www.eeworm.com/read/307337/13723899
vhd qdjb.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY QDJB IS
PORT(CLR:IN STD_LOGIC;
A,B,C,D:IN STD_LOGIC;
A1,B1,C1,D1:OUT STD_LOGIC;
STATES:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);