cont60.vhd

来自「用 VHDL语言实现闹钟功能」· VHDL 代码 · 共 43 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cont60 is
  port(ci     :in   std_logic;
       nreset :in   std_logic;
       load   :in   std_logic;
       d      :in   std_logic_vector(7 downto 0);
       clk    :in   std_logic;
       co     :out  std_logic;
       ql     :buffer  std_logic_vector(3 downto 0);
       qh     :buffer  std_logic_vector(3 downto 0));
end cont60;

architecture behave of cont60 is
begin
  co<='1'when(qh="0101" and ql="1001" and ci='1') else '0';

    process(clk,nreset)
          begin 
              if(nreset='0') then
                            qh<="0000";
                            ql<="0000";
                 elsif(clk'event and clk='1') then
                    if(load='1') then
                        qh<=d(7 downto 4);
                        ql<=d(3 downto 0);
                      elsif(ci='1') then
                       if(ql=9)  then
                          ql<="0000";
                          if(qh=5) then
                            qh<="0000";
                          else qh<=qh+1;
                          end if;
                        else
                            ql<=ql+1;
                       end if;
                     end if;
               end if;
       end process;
end behave;