speakera.vhd

基于VHDL的乐曲演奏硬件电路,基于AT的FPGA,由Quartus2编译通过

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ; 

ENTITY Speakera IS
PORT ( clk:  IN STD_LOGIC ;
       Tone: IN STD_LOGIC_VECTOR(10 DOWNTO 0);
       SpkS:OUT STD_LOGIC);
END ;

ARCHITECTURE one OF Speakera IS
SIGNAL PreCLK,FullSpks:STD_LOGIC;
BEGIN
 DivideCLK: PROCESS(clk)
  VARIABLE Count4:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
 PreCLK<='0';
 IF Count4>11 THEN PreCLK<='1'; Count4:="0000";
 ELSIF clk'EVENT AND clk='1' THEN Count4:=Count4+1;
 END IF;
END PROCESS;

GenSpks:PROCESS(PreCLK,Tone)
VARIABLE Count11: STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
 IF PreCLK'EVENT AND PreCLK='1' THEN
  IF Count11=16#7FF# THEN Count11:=Tone; FullSpks<='1';
   ELSE Count11:=Count11 +1; FullSpks<='1';
  end IF;
 END IF;
END PROCESS;

DelaySpks: PROCESS(FullSpks)
VARIABLE Count2:STD_LOGIC;
BEGIN
IF FullSpks'EVENT AND FullSpks='1' THEN  Count2:=NOT Count2;
 IF Count2='1' THEN SpkS<='1';
  ELSE  SpkS<='0';
  END IF;
END IF;
END PROCESS;

END ;