usb_fpga.vhd

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

ENTITY USB_FPGA IS
	GENERIC (
		FIFOLENTH	: integer := 1024; 	--FIFO长度2048
		FIFOWITH	: integer := 16;	--FIFO宽度------------8----16---
		PACKAGENUM	: integer := 256	--FIFO单个数据包长度--512--256--
	);
	PORT
	(
		gclk		: IN STD_LOGIC ;
		RESETFPGA 	: IN STD_LOGIC ;
--		FX2 SLAV FIFO 		
		FX2FD		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0) ;
		FX2ADR		: IN STD_LOGIC_VECTOR (8 DOWNTO 0) ;	
		
--		FX2WE		: IN STD_LOGIC ;
--		FX2CE		: IN STD_LOGIC ;
--		FX2OE		: IN STD_LOGIC ;
--		FX2DIR		: IN STD_LOGIC ;
		CTL0_FLAGA	: IN STD_LOGIC ;
		CTL1_FLAGB	: IN STD_LOGIC ;
		CTL2_FLAGC	: IN STD_LOGIC ;
		CTL3		: IN STD_LOGIC ;
		CTL4		: IN STD_LOGIC ;
		CTL5		: IN STD_LOGIC ;
		
		RDY0_SLRD	: OUT STD_LOGIC ;
		RDY1_SLWR	: OUT STD_LOGIC ;
		RDY2		: OUT STD_LOGIC ;
		RDY3		: OUT STD_LOGIC ;
		RDY4		: OUT STD_LOGIC ;
		RDY5		: OUT STD_LOGIC ;
		
		SRAMFD		: BUFFER STD_LOGIC_VECTOR (15 DOWNTO 0) ;
		SRAMADR		: OUT STD_LOGIC_VECTOR (17 DOWNTO 0) ;	
		SRAMWE		: OUT STD_LOGIC ;
		SRAMCE		: OUT STD_LOGIC ;
		SRAMOE		: OUT STD_LOGIC ;
		SRAMUB		: OUT STD_LOGIC ;
		SRAMLB		: OUT STD_LOGIC ;
		
		LED1		: OUT STD_LOGIC ;
		LED2		: OUT STD_LOGIC ;
		LED3		: OUT STD_LOGIC ;
		LED4		: OUT STD_LOGIC ;
		
		KEY1		: IN STD_LOGIC ;
		KEY2		: IN STD_LOGIC ;
		KEY3		: IN STD_LOGIC ;
		KEY4		: IN STD_LOGIC
	);
END USB_FPGA;

ARCHITECTURE ARC_USB_FPGA OF USB_FPGA IS

--FIFO
TYPE fifo_arry IS ARRAY(0 to (FIFOLENTH-1)) OF bit_vector((FIFOWITH-1) DOWNTO 0);
SIGNAL fifomemory:fifo_arry;
SIGNAL fifowraddr,fifordaddr	: NATURAL RANGE 0 TO (FIFOLENTH-1) ;
SIGNAL fifowrclk,fifordclk		: STD_LOGIC ;
SIGNAL fifowren,fiforden,fifooe	: STD_LOGIC ;
SIGNAL fifoef,fifoff	: STD_LOGIC ;
SIGNAL fiforeset	: STD_LOGIC ;

SIGNAL data2usb,data2fpga	: STD_LOGIC_VECTOR((FIFOWITH-1) DOWNTO 0) ;
SIGNAL rden,wren		: STD_LOGIC ;
SIGNAL led2buf,led4buf	: STD_LOGIC ;

BEGIN

SRAMADR <= "000000000" & FX2ADR;

LED1 <= KEY1;
--LED2 <= KEY2;
LED2 <= led2buf;
LED3 <= KEY3;
--LED4 <= KEY4;
LED4 <= led4buf;

fifowrclk <= gclk;
fifordclk <= gclk;
fifowren <= CTL0_FLAGA ;
fiforden <= CTL1_FLAGB ;
fifooe <= CTL2_FLAGC ;
RDY0_SLRD <= fifoef ;
RDY1_SLWR <= fifoff ;
fiforeset <= RESETFPGA ;

data2fpga <= FX2FD;

PROCESS(fiforeset,fifowrclk,fifowren)
BEGIN
IF(fiforeset = '0') THEN
	fifowraddr <= 0;
	led2buf <= '1';
ELSIF(fifowrclk'event AND fifowrclk='1') THEN
	IF(fifowren = '0') THEN		
		fifomemory(fifowraddr) <= to_bitvector(data2fpga);
		IF (fifowraddr>=fifowraddr'high) THEN
			fifowraddr<=0;
		ELSE
			fifowraddr<=fifowraddr+1;
		END IF;	
		
		IF((fifowraddr=511) AND (data2fpga="1111111111111110")) THEN 
			led2buf <= '0';
		ELSIF(fifowraddr=(FIFOLENTH-1)) THEN 
			led2buf <= '1';
		END IF;	
		
	END IF;
END IF;		
END PROCESS;

PROCESS(fiforeset,fifordclk,fiforden,fifooe)
BEGIN
IF(fiforeset = '0') THEN
	fifordaddr <= 0;
	led4buf <= '1';
ELSIF(fifordclk'event AND fifordclk='1') THEN
	IF(fiforden = '0') THEN
		data2usb <= to_stdlogicvector(fifomemory(fifordaddr));			
		IF(fifordaddr>=fifordaddr'high) THEN
			fifordaddr<=0;
		ELSE
			fifordaddr<=fifordaddr+1;
		END IF;		

		IF(fifordaddr=511) THEN 
			led4buf <= '0';
		ELSIF(fifordaddr=(FIFOLENTH-1)) THEN 
			led4buf <= '1';
		END IF;	
	END IF;
	IF(fifooe = '1') THEN
		FX2FD <= "ZZZZZZZZZZZZZZZZ" ;
	ELSE
		FX2FD <= data2usb;
	END IF;		
END IF;		
END PROCESS;

PROCESS(fiforeset,fifowraddr,fifordaddr)
BEGIN
IF(fiforeset = '0') THEN
	fifoef <= '1';
	fifoff <= '1';
ELSE
	IF(fifowraddr = fifordaddr) THEN
		fifoef <= '0';
		fifoff <= '1';
	ELSIF(fifowraddr>fifordaddr) THEN
		IF((fifowraddr - fifordaddr) >= 1023 ) THEN
			fifoef <= '1';
			fifoff <= '0';			
		ELSE
			fifoef <= '1';
			fifoff <= '1';
		END IF;
	ELSE
		fifoef <= '1';
		fifoff <= '1';				
	END IF;
END IF;		
END PROCESS;

END ARC_USB_FPGA;