代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/318822/13471600
vhd add8_3.vhd
library ieee;
use ieee.std_logic_1164.all;
entity add8_3 is
port(
a: in std_logic_vector( 7 downto 0);
b: in std_logic;
cont: in std_logic;
ci: in std_logic_vector(6 downto 0);
www.eeworm.com/read/317739/13498897
bak led.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY led IS
PORT(clk:IN STD_LOGIC;
rst:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END l
www.eeworm.com/read/317739/13498898
vhd led.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY led IS
PORT(clk:IN STD_LOGIC;
rst:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END l
www.eeworm.com/read/317516/13503541
txt cpld源程序注释.txt
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY GDB IS
PORT
(
clk
www.eeworm.com/read/317516/13503563
vhd gdb.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY GDB IS
PORT
(
clk
www.eeworm.com/read/317239/13506912
vhd calculate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity calculate is
port(
clk:in std_logic;
lockin: in std_logic;
datain: in
www.eeworm.com/read/317239/13507087
vhd calculate.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity calculate is
port(
clk:in std_logic;
lockin: in std_logic;
datain: in
www.eeworm.com/read/317113/13510445
vhd sequence.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sequence is
port(reset,clk:in std_logic;
FLAGS:in std_logic_vector(1 downto 0);
C24,C25:in std_logic;
www.eeworm.com/read/316203/13528457
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/316203/13528458
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in