sequence.vhd

来自「实现了CPU的基本功能」· VHDL 代码 · 共 64 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sequence is
port(reset,clk:in std_logic;
     FLAGS:in std_logic_vector(1 downto 0);
     C24,C25:in std_logic;
     CBR_DATA:in std_logic_vector(2 downto 0);
     IR_DATA:in std_logic_vector(7 downto 0);
     CAR:buffer std_logic_vector(7 downto 0)
);
end entity;
architecture sequence_arc of sequence is
begin
process(reset,clk,C24,C25,CBR_DATA)
begin
if reset='1' then
     CAR<="00000000";
   elsif clk'event and clk='1' then
       if C24='1' then 
          if FLAGS(1)='1' then
               CAR<="00000000";
             else
               CAR<="00101011";
          end if;
         elsif C25='1' then
          if FLAGS(1)='1' then
               CAR<="00000000";
             else
               CAR<="00110010";
          end if;
       end if;
       case CBR_DATA is 
           when "001"=>CAR<=CAR+1;
           when "100"=>CAR<="00000000";
           when "010"=>
                case IR_DATA is
                    when "00000000"=>CAR<="00000101";
                    when "00000001"=>CAR<="00001010";
                    when "00000010"=>CAR<="00001101";
                    when "00000011"=>CAR<="00010010";
                    when "00000100"=>CAR<="00010111";
                    when "00000101"=>CAR<="00011100";
                    when "00000110"=>CAR<="00100001";
                    when "00000111"=>CAR<="00100010"; 
                    when "00001000"=>CAR<="00100011";
                    when "00001001"=>
                          if FLAGS(0)='1' then
                                 CAR<="00100101";
                              else 
                                 CAR<="00100100";
                          end if;
                    when "00001010"=>CAR<="00100101";
                    when "00001011"=>CAR<="00100110";
                    when "00001100"=>CAR<="00101101";
                    when "00001101"=>CAR<="00000000";
                    when others=>null;
                end case;
           when others=>null;
       end case;
end if;
end process;
end sequence_arc;