calculate.vhd

一个自己编写的这次2008北京市电子竞赛VHDL源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity calculate is
	port(
		clk:in std_logic;
		lockin: in std_logic;
		datain: in std_logic_vector(7 downto 0);
		datamax: out std_logic_vector(7 downto 0);
		datamin: out std_logic_vector(7 downto 0);
		datapp: out std_logic_vector(7 downto 0);
		en: in std_logic;
		clkk:out std_logic
	);
end entity calculate;

architecture one of calculate is

signal max:std_logic_vector(7 downto 0); 
signal min:std_logic_vector(7 downto 0);
signal pp: std_logic_vector(7 downto 0);
signal buffmax:std_logic_vector(7 downto 0);
signal buffmin:std_logic_vector(7 downto 0);
signal clko:std_logic;
signal i: std_logic_vector(17 downto 0);

begin	
	datamax<=max;
	datamin<=min;
	datapp<=pp;
	clkk<=clko;
	maxmax:process(lockin,clko)
		variable i:integer:=0; 
		begin
		if(clko 'event and clko='1') then max<="00000000";end if;
		if(lockin 'event and lockin='0') then
			buffmax<=datain;
			if(en='0') then 
				max<="00000000"; 
			elsif(i=0) then 
			    max<=datain;
			    i:=i+1;
			elsif(buffmax>max) then 
				max<=buffmax; 
			end if;	
		end if;		
	end process maxmax;

	minmin:process(lockin,clko)
		variable i:integer:=0; 
		begin
		if(clko 'event and clko='1') then min<="11111111";end if;
		if(lockin 'event and lockin='0') then
			buffmin<=datain;
			if(en='0') then 
				min<="11111111";
			elsif(i=0) then
				min<=datain;
				i:=i+1;
			elsif(buffmin<min) then 
				min<=buffmin; 
			end if;	
		end if;
	end process minmin;

	pppp:process(en,max,min,clko)
	begin
		if(clko 'event and clko='1') then pp<="00000000";end if;
		if(en='0') then pp<="00000000"; end if;
		pp<=max-min;
	end process pppp;
	
	clock:process(clk)
	begin
		if(clk 'event and clk='1') then
			i<=i+1;
			clko<=i(17);
		end if;
	end process clock;

end one;