add8_3.vhd

来自「application of a galois field multiplica」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;

entity add8_3 is
    port(
    a: in std_logic_vector( 7 downto 0);
    b: in std_logic;
    cont: in std_logic;
    ci: in std_logic_vector(6 downto 0);
    si: in std_logic_vector(6 downto 0);
    co: out std_logic_vector(6 downto 0);
    so: out std_logic_vector(7 downto 0));
end entity add8_3;

architecture add8_3_rtl of add8_3 is
    begin
        so(0) <= (a(0) and b) xor si(0) xor ci(0);
        co(0) <= (((a(0) and b) and cont) and si(0)) or (ci(0)  and ((a(0) and b) or si(0))) ;
        
        so(1) <= (a(1) and b) xor si(1) xor ci(1);
        co(1) <= (((a(1) and b) and cont) and si(1)) or (ci(1)  and ((a(1) and b) or si(1)));
        
        so(2) <= (a(2) and b) xor si(2) xor ci(2);
        co(2) <= (((a(2) and b) and cont) and si(2)) or (ci(2)  and ((a(2) and b) or si(2)));
        
        so(3) <= (a(3) and b) xor si(3) xor ci(3);
        co(3) <= (((a(3) and b) and cont) and si(3)) or (ci(3)  and ((a(3) and b) or si(3)));
        
        so(4) <= (a(4) and b) xor si(4) xor ci(4);
        co(4) <= (((a(4) and b) and cont) and si(4)) or (ci(4)  and ((a(4) and b) or si(4)));
        
        so(5) <= (a(5) and b) xor si(5) xor ci(5);
        co(5) <= (((a(5) and b) and cont) and si(5)) or (ci(5) and cont and ((a(5) and b) or si(5)));
        
        so(6) <= (a(6) and b) xor si(6) xor ci(6);
        co(6) <= (((a(6) and b) and cont) and si(6)) or (ci(6)  and ((a(6) and b) or si(6)));
        
        so(7) <= a(7) and b;
        
         
end architecture add8_3_rtl;