📄 led.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY led IS
PORT(clk:IN STD_LOGIC;
rst:IN STD_LOGIC;
q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END led;
ARCHITECTURE one OF led IS
TYPE STATE IS(s0,s1,s2,s3);
SIGNAL present :STATE;
SIGNAL q1:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk,rst)
BEGIN
IF rst='0'then
present<=s0;
q1<=(OTHERS=>'0');
ELSIF clk'event AND clk='1'THEN
CASE present IS
WHEN s0=>IF q1="0000"THEN
q1<="1000";
ELSE
IF count="0011"THEN
count<=(OTHERS=>'0');
q1<="0001";
present<=s1;
ELSE q1<=q1(0)&q1(3 DOWNTO 1);
count<=count+1;
present<=s0;
END IF;
END IF;
WHEN s1=>IF count="0011"THEN
count<=(others=>'0');
q1<="1001";
present<=s2;
ELSE q1<=q1(2 DOWNTO 0)&q1(3);
count<=count+1;
present<=s1;
END IF;
WHEN s2=>IF count="0011"THEN
count<=(others=>'0');
q1<="0110";
present<=s3;
ELSE q1(3 DOWNTO 2)<=q1(2)&q1(3);
q1(1 DOWNTO 0)<=q1(0)&q1(1);
count<=count+1;
present<=s2;
END IF;
WHEN s3=>IF count="0011"THEN
count<=(others=>'0');
q1<="1000";
present<=s0;
ELSE q1(3 DOWNTO 2)<=q1(2)&q1(3);
q1(1 DOWNTO 0)<=q1(0)&q1(1);
count<=count+1;
present<=s3;
END IF;
END CASE;
END IF;
END PROCESS;
q<=q1;
END;
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