代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/449907/7494574
vhd minute.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY minute IS
PORT(CP,EN,EN2,Rd:IN STD_LOGIC;
CO: OUT STD_LOGIC;
www.eeworm.com/read/449134/7517900
vhd jishuqi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishuqi is
port (
clk : in std_logic;
en : in std_logic;
clr: in
www.eeworm.com/read/448593/7529104
txt state_moor_mealy.txt
-- State Machine with Moore and Mealy outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/448593/7529105
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/448593/7529109
txt 莫尔型状态机2.txt
-- Moore State Machine with Concurrent Output Logic
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore1 is port(
clk, rst:
www.eeworm.com/read/448593/7529110
txt 莫尔型状态机1.txt
-- Moore State Machine with explicit state encoding
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity moore2 is port(
clk, rst:
www.eeworm.com/read/446897/7563102
txt 新建 文本文档.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xin is
port(a:std_logic_vector(39 downto 0);
clk,cs:in std_logic;
ao:out std_logic_vector(15 downto 0);
int
www.eeworm.com/read/444928/7602593
vhd shift.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIFT is
PORT(
CP,Rd,LD,DI:IN STD_LOGIC;
D:IN STD_LOGIC_VECTO
www.eeworm.com/read/444248/7615738
vhd cd.vhd
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cd is
port(clk:in std_logic;
ah:in std_logic_vector(3 downto 0);
qq:out std_logi
www.eeworm.com/read/444248/7615740
vhd cd_1.vhd
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cd_1 is
port(clk:in std_logic;
ah:in std_logic_vector(3 downto 0);
qq:out std_lo