新建 文本文档.txt

本源码是基于CPLD的40路数字信号采集采集一组数据提交单片机处理并受单片机控制

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity xin is
port(a:std_logic_vector(39 downto 0);
	clk,cs:in std_logic;
	ao:out std_logic_vector(15 downto 0);
	int:out std_logic);
end xin;
architecture a of xin is 
signal ints:std_logic;
signal cou:std_logic_vector(2 downto 0);
begin
process(a,clk,cs)
variable s:std_logic_vector(39 downto 0);
--variable cou:std_logic_vector(2 downto 0); 
--variable ints:std_logic;
begin
--if (rest='1')then
	if(cs='0')then
		ints<='1';
		if(clk'event and clk='1')then
			cou<=cou+1;
			if(cou=2)then
				cou<="000";
			end if;
			case cou is
			when "000"=>ao<=s(39 downto 24);
			when "001"=>ao<=s(23 downto 8);
			when "010"=>ao<=s(7 downto 0)&"11111111";
		--	when "100"=>ao<=s(31 downto 16);
		--	when "101"=>ao<=s(15 downto 0);
			when others=>null;
			end case;
		end if;
	else
		cou<="000";
		ao<=(others=>'Z');
		if((not a)>0)then
		ints<='0';
		else 
		s:=s;
		end if;
	end if;
--else
--	ints:='1';
--	ao<=(others=>'Z');
--	cou:="000";
--end if;
int<=ints;
if(ints'event and ints='0')then
	s:=a;
end if;
end process;
end a;