📄 cd.vhd
字号:
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cd is
port(clk:in std_logic;
ah:in std_logic_vector(3 downto 0);
qq:out std_logic_vector(15 downto 0));
end cd;
architecture behav of cd is
constant w:integer :=15;
signal q:std_logic_vector(15 downto 0);
begin
process(clk)
variable flag:bit_vector(2 downto 0) :="000";
variable jp1:std_logic :='0';
begin
if clk'event and clk='1' then
if flag="000" then
q<='1' & q(w downto 1);
if q(1)='1' and ah="1111" then
flag:="001";
end if;
elsif flag="001" then
q<=q(w-1 downto 0) & '0';
if q(14)='0' and ah="0000" then
flag:="010";
end if;
elsif flag="010" then
q<="0000000000000000";
flag:="000";
end if;
end if;
qq<=q;
end process;
end behav;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -