📄 shift.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SHIFT is
PORT(
CP,Rd,LD,DI:IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(0 TO 7);
DO:OUT STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(0 TO 7)
);
END SHIFT;
ARCHITECTURE A OF SHIFT IS
SIGNAL QN:STD_LOGIC_VECTOR(0 TO 7);
BEGIN
PROCESS(CP,Rd,LD)
BEGIN
IF Rd='0'THEN
QN<="00000000";
ELSE IF(CP'EVENT AND CP='1')THEN
IF LD='0'THEN
QN<=D;
ELSE
QN(0)<=DI;
FOR I IN 0 TO 6 LOOP
QN(I+1)<=QN(I);
END LOOP;
END IF;
END IF;
END IF;
END PROCESS;
DO<=QN(7);
Q<=QN;
END A;
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