📄 cd_1.vhd
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library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cd_1 is
port(clk:in std_logic;
ah:in std_logic_vector(3 downto 0);
qq:out std_logic_vector(15 downto 0));
end cd_1;
architecture behav of cd_1 is
constant w:integer :=15;
signal q:std_logic_vector(15 downto 0);
begin
process(clk)
variable flag:bit_vector(2 downto 0) :="000";
variable jp1:std_logic :='0';
begin
if clk'event and clk='1' then
if flag="000" then
q(w downto 8)<=q(w-1 downto 8)&'1';
q(w-8 downto 0)<='1'& q(w-8 downto 1);
if q(1)='1' and ah="0111" then
flag:="001";
end if;
elsif flag="001" then
q(w downto 8)<='0'& q(w downto 9);
q(w-8 downto 0)<=q(w-9 downto 0)&'0';
if q(6)='0' and ah="1111" then
flag:="010";
end if;
elsif flag="010" then
q<="0000000000000000";
flag:="000";
end if;
end if;
qq<=q;
end process;
end behav;
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