代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
代码结果 10,000
www.eeworm.com/read/457415/7325749
vhd filt_test_system.vhd
-- Copyright (C) 2004-2005 Digish Pandya
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License a
www.eeworm.com/read/456278/7352820
vhd andarith.vhd
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likel
www.eeworm.com/read/456278/7352830
vhd reg16b.vhd
-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likel
www.eeworm.com/read/456114/7357361
vhd cnt10b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10B IS
PORT(LD,CLK,RST,EN:IN STD_LOGIC;
Q:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CQ:OUT STD_LOGIC_VECTOR(3 DO
www.eeworm.com/read/454493/7388286
vhd comcoun.vhd
--comcoun.vhd 7 segment com scan counter
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comcoun is
port(
clk : in std_logic;--synchronouse clock
f1k
www.eeworm.com/read/454373/7392986
vhd lcok.vhd
library ieee;
use ieee.std_logic_1164.all;
entity lock is
port(
key,rst,change: in std_logic;
code:in std_logic_vector(7 downto 0);
led1,led2: out std_logic
);
end lock;
architecture
www.eeworm.com/read/453834/7407501
vhd jishu10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu10 is
port(clk,clr,set:in std_logic;
q:out std_logic_vector(3 downto 0));
end jishu10;
www.eeworm.com/read/453698/7414033
vhd tiaozhi.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity tiaozhi is
port(clk:in std_logic;
datai_1,dataq_1:in std_logic;
q1,q2:in std_
www.eeworm.com/read/453409/7420965
vhd ten.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ten is
port(reset,clk :in std_logic;
q :out std_logic_vector(3 downto 0));
end ten;
arch
www.eeworm.com/read/453409/7421014
vhd zhengshu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zhengshu is
port(clk,reset,stop :in std_logic;
enn :out std_logic;
shi_1,ge_0