tiaozhi.vhd

扩跳频通信在QUARTUS7.0开发环境下的VHDL源程序及总体框图实现

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;
entity tiaozhi is
port(clk:in std_logic;
	datai_1,dataq_1:in std_logic;
	q1,q2:in std_logic_vector(9 downto 0);
	Iq,Qq:out std_logic_vector(9 downto 0));
end;

architecture one of tiaozhi is
signal tempi,tempq:std_logic_vector(9 downto 0);

begin

process(clk)
begin
if clk'event and clk='1' then
	if datai_1='0' then
		tempi<="1000000000"-q1;
	else tempi<=q1;
	end if;
end if;
end process;

process(q2,dataq_1)
begin
if clk'event and clk='1' then
	if dataq_1='0' then
		tempq<="1000000000"-q2;
	else tempq<=q2;
	end if;
end if;
end process;

Iq<=tempi;
Qq<=tempq;

end;