📄 zhengshu.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zhengshu is
port(clk,reset,stop :in std_logic;
enn :out std_logic;
shi_1,ge_0 :out std_logic_vector(3 downto 0));
end zhengshu;
architecture cnt_100_x of zhengshu is
signal shi,ge:std_logic_vector(3 downto 0);
begin
process(reset,clk,stop)
begin
if(reset='1') then
shi<="0000";ge<="0000";
else if(clk'event and clk='1') then
ge<="0101";
if(ge=9) then ge<="0000";
if (shi=9) then shi<="0000";
else shi<=shi+1;
end if;
else ge<=ge+1;
end if;
if(shi>1) then
enn<='1';
end if;
if(stop='1') then
shi<=shi;
ge<=ge;
end if;
if(shi=9 and ge=9) then
shi<="0000";
ge<="0000";
end if;
end if;
end if;
shi_1<=shi;
ge_0<=ge;
end process;
end cnt_100_x;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -