reg16b.vhd

VHDL实现的8位乘法器

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- Generated by Quartus II Version 5.1 (Build Build 213 01/19/2006)
-- Created on Sat Mar 29 10:36:11 2008

LIBRARY ieee;
USE ieee.std_logic_1164.all;


--  Entity Declaration

ENTITY REG16B IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		clk : IN STD_LOGIC;
		clr : IN STD_LOGIC;
		d : IN STD_LOGIC_VECTOR(8 downto 0);
		q : OUT STD_LOGIC_VECTOR(15 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END REG16B;


--  Architecture Body

ARCHITECTURE REG16B_architecture OF REG16B IS
signal r16s:std_logic_vector(15 downto 0);
	
BEGIN
 process(clr,clk)
  begin
   if clr='1' then
      r16s<="0000000000000000";
   elsif rising_edge(clk) then
      r16s(6 downto 0)<=r16s(7 downto 1);
      r16s(15 downto 7)<=d;
   end if;
 end process;
 q<=r16s;
END REG16B_architecture;