📄 lcok.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity lock is
port(
key,rst,change: in std_logic;
code:in std_logic_vector(7 downto 0);
led1,led2: out std_logic
);
end lock;
architecture lock of lock is
type state_type is(s0,s1,s2);
begin
process(rst,key)
variable state: state_type:=s0;
variable temp:std_logic_vector(7 downto 0):="00000001";
begin
if rst = '0' then
state := s0;
temp:="00000001";
led1<='1';
led2<='0';
elsif(key'event and key = '1' )then
case state is
when s0 => if temp=code then
state:=s1;
else
state:=s0;
end if;
when s1 =>
if change = '1' then state:=s2;
end if;
if change = '0' then state:=s0;
end if;
when s2 =>
temp:=code;
state:=s0;
end case;
end if;
if(state = s0)then
led1<='1';
led2<='0';
elsif(state = s1)then
led1<='0';
led2<='1';
else
led1<='1';
led2<='1';
end if;
end process;
end lock;
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