代码搜索:Interface

找到约 10,000 项符合「Interface」的源代码

代码结果 10,000
www.eeworm.com/read/331096/12851012

vhd mem_interface_top_test_bench_0.vhd

------------------------------------------------------------------------------- -- Copyright (c) 2005 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ---
www.eeworm.com/read/331096/12851016

vhd mem_interface_top_tap_ctrl_0.vhd

------------------------------------------------------------------------------- -- Copyright (c) 2005 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ---
www.eeworm.com/read/331096/12851025

vhd mem_interface_top_addr_gen_0.vhd

------------------------------------------------------------------------------- -- Copyright (c) 2005 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ---
www.eeworm.com/read/331096/12851042

vhd mem_interface_top_rd_data_0.vhd

------------------------------------------------------------------------------- -- Copyright (c) 2005 Xilinx, Inc. -- This design is confidential and proprietary of Xilinx, All Rights Reserved. ---
www.eeworm.com/read/239116/13302442

qsf compact_flash_ide_hard_disk_interface.qsf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/239116/13302450

qws compact_flash_ide_hard_disk_interface.qws

[ProjectWorkspace] ptn_Child1=Frames ptn_Child2=ActionPoints [ProjectWorkspace.Frames] ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 ptn_Child2=Document-1
www.eeworm.com/read/239116/13302464

qpf compact_flash_ide_hard_disk_interface.qpf

# Copyright (C) 1991-2005 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any
www.eeworm.com/read/323413/13340937

sdc autoconstraint_spi_master_interface_bt_top.sdc

#Begin clock constraint define_clock -name {b:spi_master_interface_bt_top|clk} -period 8.805 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 4.403 -route 0.000 #End clock constraint #Begin
www.eeworm.com/read/323413/13340985

v spi_master_interface_bt_top_tb.v

module spi_master_interface_bt_top_tb; reg clk,reset; wire tran_done,load_rr,config_done,tr_load,tx_empty, rec_full,int_n,wr_tr_en,start,miso,mosi,sck, spi_start; wire [7:0]s