mem_interface_top_addr_gen_0.vhd

DDR控制器 已通过FPGA 验证 大家不要错过哦

-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_addr_gen.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: The address for the memory and the various user commands can be given through 
--		this module. It instantiates the block RAM which stores all the information 
--		in particular sequence. The data stored should be in a sequence starting from
--		LSB: column address, row address, bank address, chip address, commands, and the
--		row conflict information.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity mem_interface_top_addr_gen is
	port     (
                    clk0		: in std_logic;
                    rst			: in std_logic;
                    bkend_wraddr_en	: in std_logic;
                    app_af_addr		: out std_logic_vector(35 downto 0);
                    app_af_WrEn		: out std_logic
                    );
end mem_interface_top_addr_gen;

architecture arch of mem_interface_top_addr_gen is

component RAMB16_S36
	generic( INIT_00 : bit_vector := X"0003C154_0003C198_0003C088_0003C0EC_00023154_00023198_00023088_000230EC";   
		 INIT_01 : bit_vector := X"00023154_00023198_00023088_000230EC_0003C154_0003C198_0003C088_0003C0EC";   
		 INIT_02 : bit_vector := X"0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC";   
		 INIT_03 : bit_vector := X"0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC";   
		 INIT_04 : bit_vector := X"0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC";   
		 INIT_05 : bit_vector := X"0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC";   
		 INIT_06 : bit_vector := X"00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC";   
		 INIT_07 : bit_vector := X"00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC";
		 INITP_00 : bit_vector := X"55555555_44444444_55555555_44444444_55555555_44444444_55555555_44444444"
		);
	port ( DO	: out std_logic_vector(31 downto 0);
	       DOP	: out std_logic_vector(3 downto 0);
	       ADDR	: in std_logic_vector(8 downto 0);
	       CLK	: in std_logic;
	       DI	: in std_logic_vector(31 downto 0);
	       DIP	: in std_logic_vector(3 downto 0);
	       EN	: in std_logic;
	       SSR	: in std_logic;
	       WE	: in std_logic
	     );
end component;



signal wr_rd_addr		: std_logic_vector(8 downto 0);
signal wr_rd_addr_en		: std_logic;

signal wr_addr_count		: std_logic_vector(5 downto 0);
signal bkend_wraddr_en_reg	: std_logic;
signal wr_rd_addr_en_reg	: std_logic;
signal bkend_wraddr_en_3r	: std_logic;
signal unused_data_in		: std_logic_vector(31 downto 0);
signal unused_data_in_p		: std_logic_vector(3 downto 0);
signal gnd			: std_logic;
signal addr_out			: std_logic_vector(35 downto 0);






begin


unused_data_in <= X"00000000";
unused_data_in_p <= "0000";
gnd <= '0';

--ADDRESS generation for Write and Read Address FIFOs

--ROM with address patterns
--512x36 mode is used with addresses 0-127 for storing write addresses and 
--addresses (128-511) for storing read addresses

-- bits [30:28]
-- read -5
-- write -4
-- lmr - 0
-- pre -2
-- ref -1
-- active -3

   
wr_rd_addr_lookup: RAMB16_S36 
generic map(   INIT_00  => X"0003C154_0003C198_0003C088_0003C0EC_00023154_00023198_00023088_000230EC",
               INIT_01  => X"00023154_00023198_00023088_000230EC_0003C154_0003C198_0003C088_0003C0EC",
               INIT_02  => X"0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC",
               INIT_03  => X"0083C154_0083C198_0083C088_0083C0EC_00823154_00823198_00823088_008230EC",
               INIT_04  => X"0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC",
               INIT_05  => X"0043C154_0043C198_0043C088_0043C0EC_00423154_00423198_00423088_004230EC",
               INIT_06  => X"00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC",
               INIT_07  => X"00C3C154_00C3C198_00C3C088_00C3C0EC_00C23154_00C23198_00C23088_00C230EC",
               INITP_00 => X"55555555_44444444_55555555_44444444_55555555_44444444_55555555_44444444")
	port map (
	       DO	=> addr_out(31 downto 0),
	       DOP	=> addr_out(35 downto 32),
	       ADDR	=> wr_rd_addr(8 downto 0),
	       CLK	=> clk0,
	       DI	=> unused_data_in(31 downto 0),
	       DIP	=> unused_data_in_p(3 downto 0),
	       EN	=> wr_rd_addr_en_reg,
	       SSR	=> gnd,
	       WE	=> gnd
	     ); 

wr_rd_addr_en <= bkend_wraddr_en;

process(clk0)
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1') then
	wr_rd_addr_en_reg <= '0';
 else
	wr_rd_addr_en_reg <= wr_rd_addr_en;
 end if;
end if;
end process;

--register backend enables 
process(clk0)
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1' ) then
	bkend_wraddr_en_reg <= '0';
	bkend_wraddr_en_3r  <= '0';
 else
	bkend_wraddr_en_reg <= bkend_wraddr_en;
	bkend_wraddr_en_3r  <= bkend_wraddr_en_reg;
 end if;
end if;
end process;

--FIFO enables
process(clk0)
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1') then
	app_af_WrEn <= '0';
 else
	app_af_WrEn <= bkend_wraddr_en_3r;
 end if;
end if;
end process;

--FIFO addresses
process(clk0) 
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1') then
	app_af_addr <= (others => '0');
 elsif(bkend_wraddr_en_3r = '1') then
	app_af_addr <= addr_out(35 downto 0);
 else
	app_af_addr <= (others => '0');
 end if;
end if;
end process;

--address input for ROM
process(clk0)
begin
if(clk0'event and clk0 = '1') then
 if(rst = '1') then
	wr_addr_count <= "111111";
 elsif(bkend_wraddr_en = '1') then
	wr_addr_count <= wr_addr_count +  '1';
 else
	wr_addr_count <= wr_addr_count;
 end if;
end if;
end process;


wr_rd_addr <= ("000" & wr_addr_count)  when (bkend_wraddr_en_reg ='1') else
		"000000000";


end arch;