spi_master_interface_bt_top_tb.v

a verilog prigram for SPI

module spi_master_interface_bt_top_tb;

   reg clk,reset;
   wire tran_done,load_rr,config_done,tr_load,tx_empty,
        rec_full,int_n,wr_tr_en,start,miso,mosi,sck,
        spi_start;
   wire [7:0]ss_n;
   
   initial
      begin
         clk=0;
         forever #10 clk=~clk;
      end
      
   initial
      begin
        reset=0;
        @(negedge clk)
        @(negedge clk)
        reset=1;
      end
      
   spi_master_interface_bt_top spi_int_top
   (.clk(clk),.reset(reset),.tran_done(tran_done),.load_rr(load_rr),
    .config_done(config_done),.tr_load(tr_load),.tx_empty(tx_empty),
    .rec_full(rec_full),.int_n(int_n),.wr_tr_en(wr_tr_en),.start(start),
    .miso(miso),.mosi(mosi),.sck(sck),.spi_start(spi_start),.ss_n(ss_n));
    
endmodule