autoconstraint_spi_master_interface_bt_top.sdc

a verilog prigram for SPI

#Begin clock constraint
define_clock -name {b:spi_master_interface_bt_top|clk} -period 8.805 -clockgroup Autoconstr_clkgroup_0 -rise 0.000 -fall 4.403 -route 0.000 
#End clock constraint

#Begin clock constraint
define_clock -name {n:spi_master_interface_bt_top|sck_inferred_clock} -period 3.731 -clockgroup Autoconstr_clkgroup_1 -rise 0.000 -fall 1.866 -route 0.000 
#End clock constraint