📄 mem_interface_top_test_bench_0.vhd
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-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.6
-- \ \ Application : MIG
-- / / Filename: mem_interface_top_test_bench_0.vhd
-- /___/ /\ Date Last Modified: Wed Jun 1 2005
-- \ \ / \Date Created: Mon May 2 2005
-- \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Test bench to compare the write and the read data and generate
-- an error flag.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
use work.mem_interface_top_parameters_0.all;
entity mem_interface_top_test_bench_0 is
port( CLK : in std_logic;
RESET : in std_logic;
WDF_ALMOST_FULL : in std_logic;
AF_ALMOST_FULL : in std_logic;
BURST_LENGTH : in std_logic_vector(2 downto 0);
READ_DATA_VALID : in std_logic;
READ_DATA_FIFO_OUT : in std_logic_vector((data_width*2 -1) downto 0);
APP_AF_ADDR : out std_logic_vector(35 downto 0);
APP_AF_WREN : out std_logic;
APP_WDF_DATA : out std_logic_vector((data_width*2 -1) downto 0);
APP_MASK_DATA : out std_logic_vector((data_mask_width*2 -1) downto 0);
APP_WDF_WREN : out std_logic;
ERROR : out std_logic
);
end mem_interface_top_test_bench_0;
architecture arch of mem_interface_top_test_bench_0 is
component mem_interface_top_cmp_rd_data_0
port( CLK : in std_logic;
RESET : in std_logic;
READ_DATA_VALID : in std_logic;
APP_COMPARE_DATA : in std_logic_vector((data_width*2 -1) downto 0);
READ_DATA_FIFO_OUT : in std_logic_vector((data_width*2 -1) downto 0);
ERROR : out std_logic
);
end component;
component mem_interface_top_backend_rom_0 is
port ( clk0 : in std_logic;
rst : in std_logic;
-- enables signals from state machine
bkend_data_en : in std_logic;
bkend_wraddr_en : in std_logic;
bkend_rd_data_valid : in std_logic;
--Write address fifo signals
app_af_addr : out std_logic_vector(35 downto 0);
app_af_WrEn : out std_logic;
--Write data fifo signals
app_Wdf_data : out std_logic_vector((data_width*2 -1) downto 0);
app_mask_data : out std_logic_vector((data_mask_width*2 -1) downto 0);
app_compare_data : out std_logic_vector((data_width*2 -1) downto 0);-- data for the backend compare logic
app_Wdf_WrEn : out std_logic
);
end component;
signal state : std_logic_vector(2 downto 0);
signal burst_count : std_logic_vector(3 downto 0);
signal write_data_en : std_logic;
signal write_addr_en : std_logic;
signal state_cnt : std_logic_vector(3 downto 0);
signal app_cmp_data : std_logic_vector((data_width*2 -1) downto 0);
signal burst_len : std_logic_vector(3 downto 0);
constant idle : std_logic_vector(2 downto 0) := "000";
constant write : std_logic_vector(2 downto 0) := "001";
constant read : std_logic_vector(2 downto 0) := "010";
begin
burst_len <= '0' & BURST_LENGTH;
-- State Machine for writing to WRITE DATA & ADDRESS FIFOs
process(CLK)
begin
if(CLK'event and CLK = '1') then
if (RESET = '1') then -- State Machine in IDLE state
write_data_en <= '0';
write_addr_en <= '0';
state <= idle;
state_cnt <= "0000";
burst_count <= "0000";
else
case state is
when "000" => -- idle
write_data_en <= '0';
write_addr_en <= '0';
if (WDF_ALMOST_FULL = '0' and AF_ALMOST_FULL = '0') then
state <= write;
burst_count <= burst_len; -- Burst length divided by 2
else
state <= idle;
burst_count <= "0000";
end if;
when "001" => -- write
if (WDF_ALMOST_FULL = '0' and AF_ALMOST_FULL = '0') then
if(state_cnt = "1000") then
state <= read;
state_cnt <= "0000";
if(burst_len = "0001") then
write_data_en <= '0';
else
write_data_en <= '1';
end if;
else
state <= write;
write_data_en <= '1';
end if;
if ((burst_count /= "0000") and (burst_len /= "0001")) then
burst_count <= burst_count - '1';
else
if(burst_len = "001") then
burst_count <= burst_len;
else
burst_count <= burst_len - '1';
end if;
end if;
if ((burst_count = "0001") and (state_cnt < "1000")) then
write_addr_en <= '1';
state_cnt <= state_cnt + '1';
else
write_addr_en <= '0';
end if;
else
write_addr_en <= '0';
write_data_en <= '0';
end if;
when "010" => -- read
if ( AF_ALMOST_FULL = '0') then
if(state_cnt = "1000") then
write_addr_en <= '0';
if (WDF_ALMOST_FULL = '0') then
state_cnt <= "0000";
state <= write;
else
state_cnt <= "0000";
state <= idle;
end if;
else
state <= read;
write_addr_en <= '1';
write_data_en <= '0';
state_cnt <= state_cnt + 1;
end if;
else
write_addr_en <= '0';
write_data_en <= '0';
end if;
when others =>
write_data_en <= '0';
write_addr_en <= '0';
state <= idle;
end case;
end if;
end if;
end process;
cmp_rd_data_00: mem_interface_top_cmp_rd_data_0 port map
( CLK => CLK,
RESET => RESET,
READ_DATA_VALID => READ_DATA_VALID,
APP_COMPARE_DATA => app_cmp_data,
READ_DATA_FIFO_OUT => READ_DATA_FIFO_OUT,
ERROR => ERROR
);
backend_rom_00: mem_interface_top_backend_rom_0 port map
( clk0 => CLK,
rst => RESET,
bkend_data_en => write_data_en,
bkend_wraddr_en => write_addr_en,
bkend_rd_data_valid => READ_DATA_VALID,
app_af_addr => APP_AF_ADDR,
app_af_WrEn => APP_AF_WREN,
app_Wdf_data => APP_WDF_DATA,
app_mask_data => APP_MASK_DATA,
app_compare_data => app_cmp_data,
app_Wdf_WrEn => APP_WDF_WREN
);
end arch;
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